Taraate Advanced HDL Synthesis and SOC Prototyping

RTL Design Using Verilog
1. Auflage 2018
ISBN: 978-981-10-8776-9
Verlag: Springer Singapore
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 307 Seiten

Reihe: Engineering (R0)

Explains SOC architecture and micro-architecture design with case studies

Covers practical scenarios and issues, helpful to both students and professionals

Discusses systems design and testing scenarios using modern FPGAs

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Taraate, Vaibbhav

Inhaltsverzeichnis

Introduction.- SOC Design.- RTL Design Guidelines.- RTL Design and Verification.- Processor cores and Architecture design.- Buses and protocols in SOC designs.- DSP Algorithms and Video Processing.- ASIC and FPGA Synthesis.- Static Timing Analysis.- SOC Prototyping.- SOC Prototyping guidelines.- Design Integration and SOC synthesis.- Interconnect delays and Timing.- SOC Prototyping and debug techniques.- Testing at the board level.

Über Autor(innen)

Vaibbhav Taraate is an Entrepreneur and Mentor at “Semiconductor Training @ Rs.1”. He holds a BE (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology Bombay (IIT Bombay) in 1999. He has over 15 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.