Taraate SystemVerilog for Hardware Description

RTL Design and Verification
1. Auflage 2020
ISBN: 978-981-15-4405-7
Verlag: Springer Singapore
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 252 Seiten

Reihe: Engineering

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Taraate, Vaibbhav

Inhaltsverzeichnis

Chapter 1: Introduction to FPGA design.- Chapter 2: Introduction to HDL.- Chapter 3:Introduction to SystemVerilog.- Chapter 4: Programming using SystemVerilog.- Chapter 5:Combinational design using SystemVerilog.- Chapter 6: Sequential design using SystemVerilog.- Chapter 7: RTL design using SystemVerilog.- Chapter 8: Verification using SystemVerilog.- Chapter 9: Design Implementation using FPGA.

Über Autor(innen)

Vaibbhav Taraate  is an entrepreneur and mentor at "Semiconductor Training @ Rs. 1". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur in 1995. He completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.