Thomas / Moorby The Verilog® Hardware Description Language
Third Auflage 1996
ISBN: 978-1-4757-2464-6
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
E-Book, Englisch, 310 Seiten, Web PDF
Reihe: Engineering (R0)
ISBN: 978-1-4757-2464-6
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
•• XVII Acknowledgments CHAPTER 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the NAND Latch 4 Module Hleral'Chy 6 The Counter 7 Components of the Counter 9 A Clock for the System 10 Tying the Whole Circuit Together 11 Using An Alternate Description of the Flip Flop 13 Behavioral Modeling 1 S A Behavioral Model of the m16 Counter 16 Mixing Structure and Behavior 18 Assignment Statements 22 Summary on Mixing Behavioral and Structural Descriptions 23 Creating a Testbench For a Module 24 Summary 2S Tutorial Guide to Formal Syntax Specification 26 Exercises 30 CHAPTER 2 Behavioral Modeling 33 Process Model 33 If-Then-Else 3S Where Does The ELSE Belong? 39 The Conditional Operator 41 Loops 41 Four Basic Loop Statements 42 Exiting Loops on Exceptional Conditions 45 Multi-way branching 46 If-Else-If 46 Case 46 Comparison of Case and If-Else-If 48 viii The Verilog Hardware Description Language Casez and Casex 49 Functions and Tasks SO Tasks 52 Functions 55 A Structural View 57 Rules of Scope and Hierarchical Names S9 Rules of Scope 60 Hierarchical Names 62 Summary 63 Exerdses 63 CHAPTER 3 Concurrent Processes 6S Concu"ent Processes 6S Events 67 Event Control Statement 67 Named Events 69 The Walt Statement 72 A Complete Producer-Consumer Handshake 74 Comparison of the Wait and While Statements 77 Comparison of Wait and Event Control Statements 78 A Concu"ent Process Example 78 Disabling Named Blocks 84 Intra-Assignment Control and Timing Events 87 Procedural Continuous Assignment 90
Zielgruppe
Research
Autoren/Hrsg.
Weitere Infos & Material
1 Verilog — A Tutorial Introduction.- 2 Behavioral Modeling.- 3 Concurrent Processes.- 4 Logic Level Modeling.- 5 Advanced Timing.- 6 Synthesis.- 7 User-Defined Primitives.- 8 Switch Level Modeling.- 9 Projects.
