Tian / Lian Entropy Coders of the H.264/AVC Standard

Algorithms and VLSI Architectures
1. Auflage 2010
ISBN: 978-3-642-14703-6
Verlag: Springer
Format: PDF
Kopierschutz: Wasserzeichen (»Systemvoraussetzungen)

E-Book, Englisch, 180 Seiten

This book presents a collection of algorithms and VLSI architectures of entropy (or statistical) codecs of recent video compression standards, with focus on the H.264/AVC standard. For any visual data compression scheme, there exists a combination of two, or all of the following three stages: spatial, temporal, and statistical compression. General readers are first introduced with the various algorithms of the statistical coders. The VLSI implementations are also reviewed and discussed. Readers with limited hardware design background are also introduced with a design methodology starting from performance-complexity analyses to software/hardware co-simulation. A typical design of the Contextbased Adaptive Binary Arithmetic Coding (CABAC) encoder is also presented in details. To support System-on-Chip design environment, the CABAC design is wrapped with a SoC-based Wishbone system bus interface.

Autoren/Hrsg.

Tian, Xiaohua

Lian, Yong

Inhaltsverzeichnis

1;Preface;5
2;Abstract;6
3;Contents;8
4;List of Figures;11
5;List of Tables;15
6;List of Abbreviations;17
7;Part I Background on Video Coding and Entropy Coding;21
7.1;1 Introduction to Video Compression;22
7.1.1;1.1 Background on Video Compression;22
7.1.2;1.2 Spectral Redundancy Reduction Techniques;23
7.1.3;1.3 Spatial Redundancy Reduction Techniques;24
7.1.3.1;1.3.1 Discrete Cosine Transform (DCT);25
7.1.3.2;1.3.2 Integer Transform (IT);27
7.1.3.2.1;1.3.2.1 The Integer Transform;27
7.1.3.2.2;1.3.2.2 Quantization and Rescaling;29
7.1.3.3;1.3.3 Discrete Wavelet Transform (DWT);30
7.1.4;1.4 Temporal Redundancy Reduction Techniques;32
7.1.4.1;1.4.1 Interframe Transform Coding;32
7.1.4.2;1.4.2 Conditional Replenishment;32
7.1.4.3;1.4.3 Motion Estimation;33
7.1.4.3.1;1.4.3.1 Full-Search Block Matching Algorithm (FBMA);33
7.1.4.3.2;1.4.3.2 Group 1: Reduction in the Number of Search Locations;36
7.1.4.3.3;1.4.3.3 Group 2: Reduction in the Number of Pixels Involved;38
7.1.4.3.4;1.4.3.4 Group 3: Reduction in the Bit-Depth of the Pixel;38
7.1.5;1.5 Statistical Redundancy Reduction Techniques;39
7.1.5.1;1.5.1 Run Length Coding (RCL);39
7.1.5.2;1.5.2 Huffman Coding;40
7.1.5.3;1.5.3 Arithmetic Coding;41
7.1.6;1.6 Introduction to Video Coding Standards;42
7.2;2 Review of CAVLC, Arithmetic Coding, and CABAC;47
7.2.1;2.1 Introduction of CAVLC;47
7.2.2;2.2 Pre-CABAC Arithmetic Coders;49
7.2.2.1;2.2.1 Q-Coder;49
7.2.2.2;2.2.2 QM Coder;50
7.2.2.3;2.2.3 MQ Coder;51
7.2.3;2.3 CABAC of H.264/AVC;51
7.2.3.1;2.3.1 Binarization;52
7.2.3.2;2.3.2 Context Modeling;53
7.2.3.3;2.3.3 Binary Arithmetic Coding (BAC);54
7.2.3.4;2.3.4 Comparisons of CABAC with Other Entropy Coders;57
7.3;3 Review of Existing Statistical Codec Designs;58
7.3.1;3.1 Acceleration Approaches for H.264/AVC Codec;58
7.3.2;3.2 CAVLC Decoder and Encoder Designs;59
7.3.2.1;3.2.1 CAVLC Decoder Designs;60
7.3.2.1.1;3.2.1.1 [Chang05];60
7.3.2.1.2;3.2.1.2 [Alle06];61
7.3.2.1.3;3.2.1.3 [Lin08a];62
7.3.2.1.4;3.2.1.4 Summary on Implementation Strategies of CAVLC Decoders;65
7.3.2.2;3.2.2 CAVLC Encoder Design;65
7.3.2.2.1;3.2.2.1 [Kim06a];66
7.3.2.2.2;3.2.2.2 [Chen06c];67
7.3.2.2.3;3.2.2.3 [Tsai06];69
7.3.2.2.4;3.2.2.4 [Chien06];70
7.3.2.2.5;3.2.2.5 [Rahman07];70
7.3.2.2.6;3.2.2.6 Summary of Implementation Strategies of CAVLC Encoder Designs;71
7.3.2.3;3.2.3 Comparisons of Synthesized CAVLC Codec Designs;72
7.3.3;3.3 CABAC Decoder and Encoder IP Designs;73
7.3.3.1;3.3.1 CABAC Decoder Designs;74
7.3.3.1.1;3.3.1.1 Binary Arithmetic Decoding (BAD);75
7.3.3.1.2;3.3.1.2 Context Model Selection and Access;75
7.3.3.1.3;3.3.1.3 Binarization Matching and SE Generation;77
7.3.3.1.4;3.3.1.4 Solutions to Pipeline Hazards of CABAC Decoding;77
7.3.3.2;3.3.2 CABAC Encoder Design;79
7.3.3.3;3.3.3 Comparisons of Synthesized CABAC Codec Designs;82
7.3.4;3.4 Summary of Implementation Strategies CABAC Encoder and Decoder;84
8;Part II Design of a Typical Entropy Coder;86
8.1;4 Design of a CABAC Encoder;87
8.1.1;4.1 Design Methodology for the SoC-Based Entropy Coder;87
8.1.1.1;4.1.1 Performance and Complexity Analysis of CABAC Encoder;89
8.1.1.2;4.1.2 Derivation of System Specifications for CABAC Encoder;92
8.1.2;4.2 HW/SW Functional Partitioning of CABAC Encoder;92
8.1.2.1;4.2.1 Analysis of Different Partitioning Schemes;93
8.1.2.1.1;4.2.1.1 Scheme 1: HW Design of CA and BAC;94
8.1.2.1.2;4.2.1.2 Scheme 2: HW Design of BN, CA, and BAC;94
8.1.2.1.3;4.2.1.3 Scheme 3: SW Implementation of Context Model Selection of CS 1 ;94
8.1.2.1.4;4.2.1.4 Scheme 4: Scheme 1 with HW Support for Residual SEs of BN and CS, Except CBF;94
8.1.2.1.5;4.2.1.5 Scheme 5: Complete HW Implementation of CABAC Encoder;95
8.1.2.2;4.2.2 Analysis on the Supporting RDO Function in HW CABAC Encoder;95
8.1.3;4.3 HW Encoder Functional Partitioning Schemes, and the Top-Level Encoder Architecture;96
8.1.3.1;4.3.1 Typical Hardware Functional Partitioning Scheme;98
8.1.3.1.1;4.3.1.1 Preliminary Partitioning;98
8.1.3.1.2;4.3.1.2 Detailed Functional Partitioning Scheme for SE Coding;99
8.1.3.1.3;4.3.1.3 Functional Partitioning of Additional Functions of CABAC Encoder;100
8.1.3.2;4.3.2 Fully Pipelined Top-Level HW CABAC Encoder Architecture;100
8.1.4;4.4 Binarization and Generation of Bin Packet;102
8.1.4.1;4.4.1 Input SE Parsing and Binarization of Unit BN;102
8.1.4.2;4.4.2 Bin Packet Generation and Serial Output of Unit BS0CS2;107
8.1.5;4.5 Binary Arithmetic Coding (BAC);108
8.1.5.1;4.5.1 A Typical Renormalization and Bit Packing Algorithm;108
8.1.5.2;4.5.2 Coding Interval Subdivision and Renormalization of Unit AR;111
8.1.5.3;4.5.3 Bit Packing of Unit BP;112
8.1.6;4.6 Additional Functions Supported by the CABAC Encoder;113
8.1.6.1;4.6.1 Context Model Initialization;113
8.1.6.2;4.6.2 RDO Operations Implemented in BAC;113
8.1.6.3;4.6.3 FWFT Internal FIFO Buffers;114
8.1.7;4.7 Summary;114
8.2;5 Efficient Architecture for Context Modeling in the CABAC Encoder;115
8.2.1;5.1 Context Model Selection;115
8.2.1.1;5.1.1 Scheme of Storage and Fast Access of Coded SEs of IC Sub-unit;116
8.2.1.1.1;5.1.1.1 Fast Access of Coded SEs of Neighboring Block or Sub-MB;118
8.2.1.1.2;5.1.1.2 Storage of Coded SEs of Reference MB;120
8.2.1.2;5.1.2 CtxIdxInc Calculation (IC) of Unit CS1;121
8.2.1.2.1;5.1.2.1 CtxIdxInc Calculation of Different SE Types;122
8.2.1.2.2;5.1.2.2 Storage of Coded SE Values During CtxIdxInc Calculation;124
8.2.1.2.3;5.1.2.3 End-of-MB Process;125
8.2.1.3;5.1.3 The Memory Access (MA) Sub-unit of Unit CS1;126
8.2.2;5.2 Unit CA: Efficient Context Model Access;128
8.2.2.1;5.2.1 Context Line Access and Local Buffering;128
8.2.2.2;5.2.2 Context RAM Access Scheme Supporting RDO-on Mode;130
8.2.2.3;5.2.3 Context Model Reallocation in Context RAM;132
8.2.3;5.3 Context State Backup and Restoration in P88 RDO Coding;133
8.2.4;5.4 Coded SE State Backup and Restoration of Unit CS1;135
8.2.5;5.5 Summary;137
8.3;6 Design of System Bus Interface and Inter-connection of SoC-Based CABAC Encoder;138
8.3.1;6.1 Introduction of the WISHBONE System Bus Specifications;138
8.3.1.1;6.1.1 Interface Signals of the WISHBONE System Bus;138
8.3.1.2;6.1.2 Types of Bus Cycles on the WISHBONE System Bus;140
8.3.1.3;6.1.3 Comparison of WISHBONE and AMBA System Buses;140
8.3.2;6.2 Design of WISHBONE System Bus Interfaces for CABAC Encoder;140
8.3.2.1;6.2.1 Functional Specifications of the WISHBONE System Bus Interfaces;141
8.3.2.2;6.2.2 Analysis of Support of WISHBONE Registered Feedback Cycles;141
8.3.2.3;6.2.3 Design of Slave Interface of WISHBONE System Bus;143
8.3.2.4;6.2.4 Design of Master Interface of WISHBONE System Bus;144
8.3.3;6.3 Design of System Bus Inter-connection;147
8.3.3.1;6.3.1 Design of WISHBONE Crossbar INTERCON;147
8.3.3.1.1;6.3.1.1 Master Connection Arbitration and Slave Input Selection;148
8.3.3.1.2;6.3.1.2 Master Input Selection and Slave cyc Signal Generation;149
8.3.3.2;6.3.2 Compact SoC-Based CABAC Encoding System with WISHBONE System Bus Inter-connection;149
8.4;7 Circuit Design, Implementation, and Verification of CABAC Encoder;152
8.4.1;7.1 Design and Verification Flow of CABAC Encoder HW IP;152
8.4.1.1;7.1.1 Steps in Designing a CABAC Encoder;152
8.4.1.2;7.1.2 Functional Verification of the CABAC Encoder;154
8.4.1.2.1;7.1.2.1 Verification at Different Design Stages;154
8.4.1.2.2;7.1.2.2 Verification of ASIC Design Flow and Approach of FPGA Prototype;155
8.4.2;7.2 Synthesis Results and Physical Design;156
8.5;8 Power Reduction Strategies, MBIST, and Design Performance Comparison;159
8.5.1;8.1 Power Reduction Strategies and Power Consumption Analysis;159
8.5.2;8.2 MBIST Circuit of Memory Block of CABAC Encoder;161
8.5.3;8.3 Performance Comparison;162
8.5.3.1;8.3.1 CABAC Encoding Speed Performance of the Encoder;163
8.5.3.1.1;8.3.1.1 Acceleration of CABAC Encoding;163
8.5.3.1.2;8.3.1.2 Constant Throughput of CABAC Encoder;164
8.5.3.1.3;8.3.1.3 Worst-Case Analysis of Proposed CABAC Encoder;165
8.5.3.2;8.3.2 Performance Comparison of Context Model Access Efficiency;165
8.5.3.2.1;8.3.2.1 Comparison of Context RAM Read and Write Access Efficiency;166
8.5.3.2.2;8.3.2.2 Efficiency of Context State Backup and Restoration (B&R) Operation;169
8.5.3.2.3;8.3.2.3 Context RAM Occupation Reduction;172
8.5.3.3;8.3.3 Performance Comparison with the State-of-the-Art CABAC Encoder Design;172
8.5.3.3.1;8.3.3.1 Function Completeness;172
8.5.3.3.2;8.3.3.2 Context RAM Access Efficiency;173
8.5.3.3.3;8.3.3.3 SoC-Based CABAC Encoder IP;174
8.6;9 Conclusions;177
9;Bibliography;181
10;Index;190