Verhelst / Dehaene Energy Scalable Radio Design

for Pulsed UWB Communication and Ranging
2009
ISBN: 978-90-481-2694-1
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 243 Seiten

Reihe: Analog Circuits and Signal Processing

Smart energy management, both at design time and at run time, is indispensable in modern radios. It requires a careful trade-off between the system's performance, and its power consumption. Moreover, the design has to be dynamically reconfigurable to optimally balance these parameters at run time, depending on the current operating conditions. Energy Scalable Radio Design describes and applies an energy-driven design strategy to the design of an energy-efficient, highly scalable, pulsed UWB receiver, suitable for low data rate communication and sub-cm ranging. This book meticulously covers the different design steps and the adopted optimizations: System level air interface selection, architectural/algorithmic design space exploration, algorithmic refinement (acquisition, synchronization and ranging algorithms) and circuit level (RTL) implementation based on the FLEXmodule-concept. Measurement results demonstrate the effectiveness and necessity of the energy-driven design strategy.

Autoren/Hrsg.

Verhelst, Marian

Dehaene, Wim

Inhaltsverzeichnis

1;Preface;7
2;Table of contents;8
3;1 Introduction and Motivation;13
3.1;Dreaming of a Smart Environment;13
3.2;Limited Energy Resources and the Energy Gap;13
3.3;Strategies to Bridge the Energy Gap;15
3.3.1;Power- and Energy-Oriented System-to-Circuit Design;15
3.3.1.1;Power Analysis and Optimization at Design Time;16
3.3.1.2;Energy Analysis and Optimization at Design Time;16
3.3.2;Energy-Efficient Wireless Communication and IR-UWB;18
3.3.2.1;Energy-per-Useful-Bit;18
3.3.2.2;Impulse Radio UltraWideband Communication;19
3.3.3;Runtime Energy Scalability;20
3.4;Book Scope and Organizational Overview;22
4;2 Adaptation of Classical Design Flow for Energy-Driven System-to-CircuitDesign;24
4.1;Introduction;24
4.2;Classical (Digital) Top–Down Design Flow: Gajski–Kuhn;25
4.2.1;Moore's Law and the Design Productivity Gap;25
4.2.2;Design Abstraction, Methodology and Reuse to Close the Gap;26
4.2.3;Gajski–Kuhn Y chart;27
4.3;Need for Energy-Driven CrossLayer Scalable System-to-Circuit Design;30
4.3.1;Need for Energy-Driven Design;30
4.3.2;Need for CrossLayer Design;31
4.3.3;Need for Design Towards Scalability;33
4.3.4;Need for Mixed-Signal System Design;34
4.4;Proposed Adaptations of the Classical Design Flow;34
4.4.1;Energy-Oriented Design Objective;34
4.4.2;CrossLayer Design Techniques;35
4.4.2.1;Use of Bottom–Up Power Estimations;36
4.4.2.2;Use of Decision Postponement;37
4.4.3;Algorithmic/Architectural-Level DSE;38
4.4.4;Derivation of Optimal Degree of Runtime Flexibility;39
4.4.5;System-Oriented Parameter Selection for Mixed Signal Design;41
4.5;Conclusion;42
5;3 System Level Specifications and Design;43
5.1;Introduction;43
5.2;System Specifications;43
5.2.1;Target Application Domains;44
5.2.2;Extracted Specifications;45
5.3;Selection of the Air Interface;47
5.3.1;Setup of the Comparison Based on EPUB;48
5.3.2;Air Interface Candidates;49
5.3.3;Selection of the Optimal Candidate;51
5.3.4;UWB Communication;53
5.3.4.1;UWB History and Regulations;53
5.3.4.2;IR-UWB Basics;55
5.3.4.3;UWB Advantages;58
5.3.4.4;Additional UWB-Related Specifications;59
5.4;Conclusion;60
6;4 Algorithmic/Architectural Design Space Exploration;61
6.1;Introduction;61
6.2;UWB Communication and Receiver Framework;63
6.3;Receiver Alternatives;67
6.3.1;FD;67
6.3.1.1;RAKE and RAKE-Like Reception;68
6.3.1.2;Averaged Template Reception;69
6.3.2;Partially Analog/Hybrid;69
6.3.2.1;Digital-To-Analog Converter Based AnalogCorrelation;69
6.3.2.2;Simplified Analog Correlation;71
6.3.2.3;Quadrature Analog Correlation;72
6.3.2.4;Transmitted Reference;74
6.3.2.5;Energy Detector;75
6.3.2.6;Flashing Receiver;75
6.3.3;Fully Analog;76
6.3.4;Receiver Summary;76
6.4;Receiver Comparison: Power, Performance, EPUB;76
6.4.1;Performance Simulation;76
6.4.1.1;Theoretical Derivation;76
6.4.1.2;Simulation Setup;79
6.4.1.3;Simulation Results;80
6.4.2;Power Estimation;81
6.4.3;Minimal EPUB;86
6.5;A/A DSE Summary;87
6.6;Further Considerations;90
6.6.1;Packet Length;90
6.6.2;Frequency Band;90
6.6.3;Technology Scaling;92
6.6.4;802.15.4a Compatibility;92
6.7;Conclusion;95
7;5 Algorithmic/Architectural Level Refinement;96
7.1;Introduction;96
7.2;Algorithm Refinement;96
7.2.1;Data Detection;97
7.2.1.1;Pulse Recovery;98
7.2.1.2;Despreading with the PN Code and Data Detection;105
7.2.1.3;Synchronization During Data Detection;107
7.2.2;Acquisition;110
7.2.2.1;Acquisition Basic Principles;110
7.2.2.2;Window and Code Alignment: Strongest Path;110
7.2.2.3;Window and Code Alignment: MultiPath;121
7.2.2.4;Effect of CO and Offset Estimation;126
7.2.2.5;VGA Training;128
7.2.2.6;End-of-Preamble;128
7.2.3;Ranging;128
7.2.3.1;Coarse Ranging Based on the Optimal IntegrationWindow;129
7.2.3.2;Ranging Refinement Based on the Energy Profile;129
7.2.3.3;Ranging Refinement Based on the Received Phase;130
7.3;Architecture Refinement;131
7.3.1;System Architecture;132
7.3.2;Back-End Architecture;133
7.3.3;Front-End Architecture;135
7.3.3.1;Deriving Front-End Building Block Specifications;135
7.4;Conclusion;141
8;6 Digital RT Level Design: Flexibility to Save Energy;143
8.1;Introduction;143
8.2;Design Based on Nested FLEXmodules;144
8.2.1;Need for Flexible, Regular, Nested Modules;144
8.2.2;FLEXmodules Offer Flexibility at Low Cost;144
8.2.2.1;Custom MicroController;145
8.2.3;Chip Architecture Based on FLEXmodules;146
8.3;Measuring and Weighing Flexibility;148
8.3.1;Difficulties in Measuring Flexibility;148
8.3.2;Alternative Measure of Flexibility;149
8.3.3;Cost of Flexibility;151
8.3.4;Benefits of Flexibility;153
8.4;Energy-Optimal Design Through Flexibility;154
8.4.1;Flexibility of FUs: Parameterized Code Generatorand Correlator;155
8.4.2;Flexibility of FLEXmodules: The ct_pr Unit;160
8.5;Intermediate Conclusion on the Flexibility–Power–PerformanceTrade-Off;167
8.6;Detailed Back-End Architecture and Design;168
8.6.1;TOP FLEXmodule;168
8.6.2;CLK_GEN FLEXmodule;169
8.6.3;COMM FLEXmodule;169
8.6.4;SE FLEXmodule;171
8.6.5;CT FLEXmodule;171
8.6.6;DD FLEXmodule;182
8.6.7;FIFOs;186
8.6.8;Clock and Power Domains;187
8.6.9;Debug;188
8.6.10;Final Back-End Implementation;189
8.6.11;Flexibility Comparison of the Implemented Design;190
8.7;Conclusion;192
9;7 Chip and System Measurements;193
9.1;Introduction;193
9.2;Back-End Measurements;193
9.2.1;Measurement Setup;193
9.2.2;Measurement Results;195
9.2.2.1;Functional Measurements;195
9.2.2.2;Energy-Efficiency and Flexibility Measurements;199
9.2.3;Back-End Measurement Summary and Possible Improvements;203
9.3;System Measurements: 3–5 GHz Band;205
9.3.1;Measurement Motivation;205
9.3.2;Measurement Setup;206
9.3.2.1;Measurement Setup Problems and Patches;208
9.3.3;Measurement Results;209
9.3.3.1;Wired Measurements;209
9.3.3.2;Wireless Measurements;212
9.3.4;3–5 GHz System Measurement Summary;214
9.4;System Measurements: 0–960 MHz Band;214
9.4.1;Measurement Setup;214
9.4.2;Measurement Results;216
9.4.2.1;Wired Measurements;216
9.4.2.2;Wireless Measurements;218
9.4.3;0–960 MHz System Measurement Summary;219
9.5;Receiver Comparison;220
9.6;Conclusion;222
10;Conclusions;225
11;Bibliography;228
12;Index;247