System-On-Chip Test Architectures

Nanometer Design for Testability Volume .
Erscheinungsjahr 2007
ISBN: 978-0-12-373973-5
Verlag: Elsevier Science

Buch, Englisch, 896 Seiten, Format (B × H): 197 mm x 241 mm, Gewicht: 1596 g

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Zielgruppe

Practitioners/Researchers in VLSI Design and Testing; Design or Test Engineers, as well as research institutes.

Autoren/Hrsg.

Wang, Laung-Terng

Stroud, Charles E

Touba, Nur A

Fachgebiete

• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik
• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnische Normen

Inhaltsverzeichnis

Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.

Über Autor(innen)

Wang, Laung-Terng
Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).