Wehmeyer / Marwedel Fast, Efficient and Predictable Memory Accesses

Optimization Algorithms for Memory Architecture Aware Compilation
2006
ISBN: 978-1-4020-4822-7
Verlag: Springer Netherland
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 258 Seiten, eBook

Speed improvements in memory systems have not kept pace with the speed improvements of processors, leading to embedded systems whose performance is limited by the memory. This book presents design techniques for fast, energy-efficient and timing-predictable memory systems that achieve high performance and low energy consumption. In addition, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds.

Zielgruppe

Research

Autoren/Hrsg.

Wehmeyer, Lars

Marwedel, Peter

Inhaltsverzeichnis

1 Abstract. 2 Introduction. 2.1 Motivation. 2.2 Contributions of this Work. 2.3 Overview. 3 Models and Tools. 3.1 Instruction Set Architecture Model. 3.2 Memory Models. 3.3 Timing Models. 3.4 Energy Models.3.5 Simulation Models. 3.6 The encc Compiler Framework. 4 Scratchpad Memory Optimizations. 4.1 Related Work. 4.2 Multi Memory Optimization. 4.3 Impact of Scratchpad Allocation Techniques on WCET. 5 Main Memory Optimizations. 5.1 Related Work. 5.2 Main Memory Power Management. 5.3 Execute-In-Place using Flash Memories. 6 Register File Optimization. 6.1 Related Work. 6.2 Implementation of the Register File. 6.3 Register Allocation and Lifetime Analysis. 6.4 Workflow and Methodology. 6.5 Benchmark Suite. 6.6 Compiler Guided Choice of Register File Size. 7 Summary. 8 Future Work. Index. References.

Über Autor(innen)

Prof. Peter Marwedel is well established within the Electronic Design Automation community, he has co-authored four books with us and also published his best-selling Embedded Systems Design (text)book with Springer.