Beck Fl. / Carro Dynamic Reconfigurable Architectures and Transparent Optimization Techniques

Automatic Acceleration of Software Execution
1. Auflage 2010
ISBN: 978-90-481-3913-2
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 177 Seiten

Dynamic Reconfigurable Architectures and Transparent Optimization Techniques presents a detailed study on new techniques to cope with the aforementioned limitations. First, characteristics of reconfigurable systems are discussed in details, and a large number of case studies is shown. Then, a detailed analysis of several benchmarks demonstrates that such architectures need to attack a diverse range of applications with very different behaviours, besides supporting code compatibility. This requires the use of dynamic optimization techniques, such as Binary Translation and Trace reuse. Finally, works that combine both reconfigurable systems and dynamic techniques are discussed and a quantitative analysis of one them, the DIM architecture, is presented.

Autoren/Hrsg.

Beck Fl., Antonio Carlos Schneider

Carro, Luigi

Inhaltsverzeichnis

1;Preface;6
2;Acknowledgements;8
3;Contents;9
4;Acronyms;13
5;Introduction;16
5.1;Challenges;16
5.2;Main Motivations;19
5.2.1;Overcoming Some Limits of the Parallelism;19
5.2.2;Taking Advantage of Combinational and Reconfigurable Logic;21
5.2.3;Software Compatibility and Reuse of Existent Binary Code;22
5.2.4;Increasing Yield and Reducing Manufacture Costs;23
5.3;This Book;25
5.4;References;25
6;Reconfigurable Systems;27
6.1;Introduction;27
6.2;Basic Principles;29
6.2.1;Reconfiguration Steps;29
6.3;Underlying Execution Mechanism;31
6.4;Advantages of Using Reconfigurable Logic;34
6.4.1;Application;36
6.4.2;An Instruction Merging Example;36
6.5;Reconfigurable Logic Classification;38
6.5.1;Code Analysis and Transformation;38
6.5.2;RU Coupling;39
6.5.3;Granularity;41
6.5.4;Instruction Types;43
6.5.5;Reconfigurability;44
6.6;Directions;44
6.6.1;Heterogeneous Behavior of the Applications;45
6.6.2;Potential for Using Fine Grained Reconfigurable Arrays;48
6.6.3;Coarse Grain Reconfigurable Architectures;52
6.6.4;Comparing Both Granularities;55
6.7;References;57
7;Deployment of Reconfigurable Systems;59
7.1;Introduction;59
7.2;Examples of Reconfigurable Architectures;60
7.2.1;Chimaera;60
7.2.1.1;RU Coupling;60
7.2.1.2;Reconfigurable System and Granularity;60
7.2.1.3;Instruction Type, Reconfiguration and Execution;61
7.2.1.4;Code Analysis and Transformation;62
7.2.1.5;Evaluation;62
7.2.2;GARP;63
7.2.2.1;RU Coupling;63
7.2.2.2;Granularity;63
7.2.2.3;Reconfigurable System;63
7.2.2.4;Instruction Type, Reconfiguration and Execution;64
7.2.2.5;Code Analysis and Transformation;65
7.2.2.6;Evaluation;65
7.2.3;REMARC;66
7.2.3.1;RU Coupling;66
7.2.3.2;Reconfigurable System and Granularity;66
7.2.3.3;Instruction Type, Reconfiguration and Execution;68
7.2.3.4;Code Analysis and Transformation;69
7.2.3.5;Evaluation;69
7.2.4;Rapid;69
7.2.4.1;RU Coupling, Reconfigurable System and Granularity;69
7.2.4.2;Instruction Type, Reconfiguration and Execution;70
7.2.4.3;Code Analysis and Transformation;70
7.2.4.4;Evaluation;70
7.2.5;Piperench (1999);71
7.2.5.1;RU Coupling;71
7.2.5.2;Reconfigurable System and Granularity;71
7.2.5.3;Instruction Type, Reconfiguration and Execution;73
7.2.5.4;Code Analysis and Transformation;74
7.2.5.5;Evaluation;74
7.2.6;Molen;75
7.2.6.1;RU Coupling, Reconfigurable System and Granularity;75
7.2.6.2;Instruction Type, Reconfiguration and Execution;75
7.2.6.3;Code Analysis and Transformation;76
7.2.6.4;Evaluation;76
7.2.7;Morphosys;77
7.2.7.1;RU Coupling, Reconfigurable System and Granularity;77
7.2.7.2;Instruction Type, Reconfiguration and Execution;79
7.2.7.3;Code Analysis and Transformation ;79
7.2.7.4;Evaluation;79
7.2.8;ADRES;80
7.2.8.1;RU Coupling;80
7.2.8.2;Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution;80
7.2.8.3;Code Analysis and Transformation ;81
7.2.8.4;Evaluation;81
7.2.9;Concise;82
7.2.9.1;RU Coupling and Granularity;82
7.2.9.2;Reconfigurable System, Instruction Type, Reconfiguration and Execution;82
7.2.9.3;Code Analysis and Transformation;83
7.2.9.4;Evaluation;83
7.2.10;PACT-XPP;83
7.2.10.1;RU Coupling;84
7.2.10.2;Reconfigurable System, Granularity, Instruction Type;84
7.2.10.3;Reconfiguration and Execution;85
7.2.10.4;Code Analysis and Transformation;86
7.2.10.5;Evaluation;86
7.2.11;RAW;87
7.2.11.1;RU Coupling;87
7.2.11.2;Reconfigurable System and Granularity;87
7.2.11.3;Instruction Type, Reconfiguration and Execution;88
7.2.11.4;Code Analysis and Transformation;88
7.2.11.5;Evaluation;88
7.2.12;Onechip;89
7.2.12.1;RU Coupling;89
7.2.12.2;Reconfigurable System and Granularity;89
7.2.12.3;Code Analysis and Transformation;90
7.2.12.4;Instruction Type, Reconfiguration and Execution;90
7.2.12.5;Evaluation;90
7.2.13;Chess;90
7.2.13.1;RU Coupling, Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution;90
7.2.13.2;Code Analysis and Transformation, and Evaluation;92
7.2.14;PRISM I;92
7.2.14.1;RU Coupling, Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution;92
7.2.14.2;Code Analysis and Transformation ;92
7.2.14.3;Evaluation;92
7.2.15;PRISM II;92
7.2.15.1;RU Coupling;93
7.2.15.2;Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution;93
7.2.15.3;Code Analysis and Transformation ;94
7.2.15.4;Evaluation;94
7.2.16;Nano;94
7.2.16.1;RU Coupling;94
7.2.16.2;Reconfigurable System, Granularity, Instruction Type, Reconfiguration and Execution;94
7.2.16.3;Code Analysis and Transformation;95
7.2.16.4;Evaluation;95
7.3;Recent Dataflow Architectures;95
7.4;Summary and Comparative Tables;97
7.4.1;Other Reconfigurable Architectures;97
7.4.2;Benchmarks;98
7.5;References;103
8;Dynamic Optimization Techniques;108
8.1;Introduction;108
8.2;Binary Translation;108
8.2.1;Main Motivations;108
8.2.2;Basic Concepts;110
8.2.3;Challenges;112
8.2.3.1;Register Mapping;112
8.2.3.2;Memory Mapped I/O;112
8.2.3.3;Atomic Instructions;112
8.2.3.4;Issues Related to the Code;113
8.2.3.5;OS Emulation;113
8.2.4;Examples;113
8.2.4.1;DAISY;115
8.2.4.2;VEST;116
8.2.4.3;DYNAMO;118
8.2.4.4;Transmeta Crusoe;119
8.2.4.5;FX!32;120
8.3;Reuse;122
8.3.1;Instruction Reuse;122
8.3.2;Value Prediction;123
8.3.3;Block Reuse;124
8.3.4;Trace Reuse;125
8.3.5;Dynamic Trace Memoization and RST;127
8.4;References;128
9;Dynamic Detection and Reconfiguration;131
9.1;Warp Processing;131
9.1.1;The Reconfigurable Array;132
9.1.2;How Translation Works;133
9.1.3;Evaluation;135
9.2;Configurable Compute Array;136
9.2.1;The Reconfigurable Array;136
9.2.2;Instruction Translator;137
9.2.3;Evaluation;140
9.3;Drawbacks;140
9.4;References;141
10;The DIM Reconfigurable System;143
10.1;Introduction;143
10.1.1;General System Overview;145
10.2;The Reconfigurable Array in Details;146
10.3;Translation, Reconfiguration and Execution;147
10.4;The BT Algorithm in Details;150
10.4.1;Data Structure;150
10.4.2;How It Works;151
10.4.3;Additional Extensions;152
10.4.4;Handling False Dependencies;154
10.4.5;Speculative Execution;155
10.5;Case Studies;157
10.5.1;Coupling the Array to a Superscalar Processor;157
10.5.2;Coupling the Array to the MIPS R3000 Processor;161
10.5.3;Final Considerations;166
10.6;DIM in Stack Machines;167
10.7;On-Going and Future Works;168
10.7.1;First Studies on the Ideal Shape of the Reconfigurable Array;168
10.7.2;Sleep Transistors;170
10.7.3;Speculation of Variable Length;171
10.7.4;DSP, SIMD and Other Extensions;171
10.7.5;Design Space to Be Explored;171
10.8;References;171
11;Conclusions and Future Trends;174
11.1;Introduction;174
11.2;Decreasing the Routing Area of Reconfigurable Systems;174
11.3;Measuring the Impact of the OS in Reconfigurable Systems;176
11.4;Reconfigurable Systems to Increase the Yield;177
11.5;Study of the Area Overhead with Technology Scaling and Future Technologies;178
11.6;Scheduling Targeting to Low-power;179
11.7;Granularity-Comparisons;179
11.8;Reconfigurable Systems Attacking Different Levels of Instruction Granularity;179
11.8.1;Multithreading;179
11.8.2;CMP;181
11.9;Final Considerations;183
11.10;References;183
12;Index;185