Bhatnagar Advanced ASIC Chip Synthesis

Using Synopsys® Design Compiler™ and PrimeTime®
Erscheinungsjahr 2012
ISBN: 978-1-4419-8668-9
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 284 Seiten, eBook

Advanced ASIC Chip Synthesis: Using Synopsys® DesignCompiler® and PrimeTime® describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-arounds described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solutions. Advanced ASIC Chip Synthesis: Using Synopsys® DesignCompiler® and PrimeTime® is intended for anyone who is involved in the ASIC design methodology, starting from RTL synthesis to final tape-out. Target audiences for this book are practicing ASIC design engineers and graduate students undertaking advanced courses in ASIC chip design and DFT techniques. From the Foreword: `This book, written by Himanshu Bhatnagar, provides a comprehensive overview of the ASIC design flow targeted for VDSM technologies using the Synopsis suite of tools. It emphasizes the practical issues faced by the semiconductor design engineer in terms of synthesis and the integration offront-end and back-end tools. Traditional design methodologies are challenged and unique solutions are offered to help define the next generation of ASIC design flows. The author provides numerous practical examples derived from real-world situations that will prove valuable to practicing ASIC design engineers as well as to students of advanced VLSI courses in ASIC design'. Dr Dwight W. Decker, Chairman and CEO, Conexant Systems, Inc., (Formerly, Rockwell Semiconductor Systems), Newport Beach, CA, USA.

Zielgruppe

Research

Autoren/Hrsg.

Bhatnagar, Himanshu

Inhaltsverzeichnis

1: Asic Design Methodology.- 1.1 Typical Design Flow.- 1.2 Chapter Summary.- 2: Tutorial.- 2.1 Example Design.- 2.2 Initial Setup.- 2.3 Pre-Layout Steps.- 2.4 Floorplanning and Routing.- 2.5 Post-Layout Steps.- 2.6 Chapter Summary.- 3: Basic Concepts.- 3.1 Synopsys Products.- 3.2 Synthesis Environment.- 3.3 Objects, Variables and Attributes.- 3.4 Finding Design Objects.- 3.5 Synopsys Formats.- 3.6 Data Organization.- 3.7 Design Entry.- 3.8 Compiler Directives.- 3.9 Chapter Summary.- 4: Synopsys Technology Library.- 4.1 Library Basics.- 4.2 Delay Calculation.- 4.3 What is a Good Library?.- 4.4 Chapter Summary.- 5: Partitioning And Coding Styles.- 5.1 Partitioning for Synthesis.- 5.2. What is RTL?.- 5.3 General Guidelines.- 5.4 Logic Inference.- 5.5 Order Dependency.- 5.6 Chapter Summary.- 6: Constraining Designs.- 6.1 Environment and Constraints.- 6.2 Advanced Constraints.- 6.3 Clocking Issues.- 6.4 Putting it Together.- 6.5 Chapter Summary.- 7: Optimizing Designs.- 7.1 Design Space Exploration.- 7.2 Total Negative Slack.- 7.3 Compilation Strategies.- 7.4 Resolving Multiple Instances.- 7.5 Optimization Techniques.- 7.6 Chapter Summary.- 8: Design For Test.- 8.1 Types of DFT.- 8.2 Scan Insertion.- 8.3 DFT Guidelines.- 8.4 Chapter Summary.- 9: Links To Layout &Amp; Post Layout Opt.- 9.1 Generating Netlist for Layout.- 9.2 Layout.- 9.3 Post-Layout Optimization.- 9.4 Future Directions.- 9.5 Chapter Summary.- 10: Sdf Generation.- 10.1 SDF File.- 10.2 SDF File Generation.- 10.3 Chapter Summary.- 11; Primetime Basics.- 11.1 Introduction.- 11.2 Tcl Basics.- 11.3 PrimeTime Commands.- 11.4 Chapter Summary.- 12: Static Timing Analysis.- 12.1 Why Static Timing Analysis?.- 12.2 Timing Exceptions.- 12.3 Disabling Timing Arcs.- 12.4 Environment and Constraints.- 12.5 Pre-Layout.- 12.6Post-Layout.- 12.7 Analyzing Reports.- 12.8 Advanced Analysis.- 12.9 Chapter Summary.