Clara High-Performance D/A-Converters

Application to Digital Transceivers
2013
ISBN: 978-3-642-31229-8
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 36, 286 Seiten

Reihe: Springer Series in Advanced Microelectronics

This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested.  With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.

Martin Clara received the M.Sc. degree in electrical engineering from Vienna University of Technology, Austria, in 1996 and the Ph.D. degree in electronics from Graz University of Technology, Austria, in 2009.In 1997 he joined Siemens Microelectronics' Design Center in Villach, Austria, as an Analog Design Engineer, mainly working on BiCMOS and CMOS linear circuits.From 2000 to 2009 he was with Infineon Technologies' Design Center in Villach,Austria, where he designed data converters, linear circuits and RF building blocks in deep-submicron and nanometer CMOS technologies.Since 2009 he is senior engineer for analog/mixed-signal and RF-design at LANTIQ's design center, based in Villach, Austria.His main interests include the implementation of low-voltage and high dynamic range analog front-ends in advanced CMOS technologies, the concept and design of highperformance data converters, as well as RF-CMOS design.

Autoren/Hrsg.

Clara, Martin

Inhaltsverzeichnis

1;Application to Digital Transceivers;4
2;Preface;6
3;Contents;10
4;Acronyms and Abbreviations;14
5;List of Symbols;16
6;Chapter 1 Introduction;24
6.1;1.1 Integrated D/A-Converters;24
6.2;1.2 DACs for Highly Integrated Transceivers;30
6.3;1.3 The Ideal D/A-Converter;34
6.3.1;1.3.1 The Non Return-to-Zero DAC;35
6.3.2;1.3.2 The Return-to-Zero DAC;37
6.4;1.4 The Current-Steering DAC;39
6.4.1;1.4.1 General Description;39
6.4.2;1.4.2 Single-Polarity and Dual-Polarity Current Cells;41
6.4.3;1.4.3 Passive and Active Output Stage;41
6.5;1.5 Array Coding;43
6.5.1;1.5.1 Unary Array;43
6.5.2;1.5.2 Binary Array;44
6.5.3;1.5.3 Segmented Array;45
7;Chapter 2 Performance Figures of D/A-Converters;48
7.1;2.1 Static Accuracy;48
7.1.1;2.1.1 Gain and Offset Error;48
7.1.2;2.1.2 Differential Nonlinearity;49
7.1.3;2.1.3 Integral Nonlinearity;50
7.2;2.2 Dynamic Performance;51
7.2.1;2.2.1 Harmonic Distortion;51
7.2.2;2.2.2 Intermodulation Distortion;52
7.2.3;2.2.3 Spurious Free Dynamic Range;53
7.2.4;2.2.4 Dynamic Range;54
7.2.5;2.2.5 Multitone Linearity;55
7.2.5.1; Missing Tone Power Ratio;56
7.2.5.2; Missing Band Power Ratio;57
7.3;2.3 Noise Performance;58
7.3.1;2.3.1 Quantization ``Noise'';58
7.3.1.1; Nyquist-rate Converter;59
7.3.1.2; Noiseshaped Converter;60
7.3.2;2.3.2 Circuit Noise;61
7.3.3;2.3.3 Jitter Noise;69
7.3.3.1; NRZ D/A-Converter;72
7.3.3.2; Return-to-Zero DAC;74
7.3.3.3; Sampling Jitter in Multitone Systems;78
7.3.3.4; Experimental verification;81
8;Chapter 3 Static Linearity;86
8.1;3.1 Limitations for the Static Linearity;86
8.1.1;3.1.1 Matching of Current Sources;87
8.1.2;3.1.2 Statistical Description of the INL;88
8.1.3;3.1.3 Statistical Description of the DNL;89
8.1.4;3.1.4 Minimum Area Requirements;91
8.1.5;3.1.5 Code-Dependent Output Impedance;97
8.2;3.2 Dynamic Element Matching Techniques;101
8.2.1;3.2.1 Clocked Level Averaging;103
8.2.2;3.2.2 Data-Weighted Averaging;104
8.2.3;3.2.3 Other DEM Techniques;105
8.3;3.3 Current Source Calibration;107
8.3.1;3.3.1 Factory Trimming;108
8.3.2;3.3.2 Self-calibration;109
8.3.3;3.3.3 Local Calibration DAC;111
8.3.4;3.3.4 Global Calibration DAC;112
8.3.5;3.3.5 Trimmable Floating Current Source;113
8.3.6;3.3.6 Dynamic Current Calibration;114
9;Chapter 4 Dynamic Linearity;119
9.1;4.1 Limitations for the Dynamic Linearity;119
9.1.1;4.1.1 Frequency-Dependent Output Impedance;119
9.1.2;4.1.2 A Generalized Switching Error Model;124
9.1.3;4.1.3 Switching Transition Mismatch;129
9.1.4;4.1.4 Charge Sharing at the Switching Node;133
9.1.5;4.1.5 A SPICE-Simulation Example;138
9.1.6;4.1.6 Other Nonlinear Effects;140
9.2;4.2 Methods to Improve the Dynamic Performance;140
9.2.1;4.2.1 Current Switch with Reduced Gate Voltage Swing;141
9.2.2;4.2.2 Source Node Bootstrapping;144
9.2.3;4.2.3 Source Node Isolation;145
9.2.4;4.2.4 Differential Quad Switching;146
9.2.5;4.2.5 Constant Digital Activity;147
9.2.6;4.2.6 Return-to-Zero and Track/Attenuate;148
9.2.7;4.2.7 Double Return-to-Zero;150
9.2.8;4.2.8 Full-Clock Interleaved Current Cells;151
10;Chapter 5 Noiseshaped D/A-Converters;154
10.1;5.1 A 14-bit Low-Power D/A-Converter;154
10.1.1;5.1.1 Converter Architecture;155
10.1.2;5.1.2 DEM Selection;156
10.1.3;5.1.3 Unit Current Cell;157
10.1.4;5.1.4 Low-Noise Biasing;159
10.1.5;5.1.5 Output Stage;159
10.1.6;5.1.6 Layout;160
10.1.7;5.1.7 Experimental Results;162
10.2;5.2 A 12-Bit/14-Bit Multistandard DAC;165
10.2.1;5.2.1 Low-OSR Noiseshaper;166
10.2.2;5.2.2 Interleaved Data Weighted Averaging;168
10.2.3;5.2.3 Converter Architecture;171
10.2.4;5.2.4 Current-Cell Design;173
10.2.5;5.2.5 Low-Noise Biasing;174
10.2.6;5.2.6 Output Stage Design;176
10.2.7;5.2.7 Layout;178
10.2.8;5.2.8 Experimental Results;180
10.3;5.3 Literature Comparison of Noiseshaped DACs;184
11;Chapter 6 Advanced Current Calibration;187
11.1;6.1 A Self-calibrated 13-Bit 100–200MS/s D/A-Converter;188
11.1.1;6.1.1 Converter Architecture;188
11.1.2;6.1.2 Trimmable PMOS Current Cell;189
11.1.3;6.1.3 Segmented Background Calibration;192
11.1.4;6.1.4 Randomized Calibration Cycle;196
11.1.5;6.1.5 Layout;200
11.1.6;6.1.6 Experimental Results;201
11.1.6.1; Noiseshaped Converter Mode;207
11.2;6.2 A 13-Bit 130–300MS/s DAC with Active Output Stage;210
11.2.1;6.2.1 Converter Architecture;211
11.2.2;6.2.2 The Current Cells;212
11.2.3;6.2.3 Direct Segment Calibration;214
11.2.4;6.2.4 Programmable Biasing;218
11.2.5;6.2.5 Push-Pull Operational Amplifier;219
11.2.6;6.2.6 Output Stage Optimization;220
11.2.7;6.2.7 Layout;222
11.2.8;6.2.8 Experimental Results;223
11.3;6.3 A Figure-of-Merit for Nyquist D/A-Converters;231
12;Chapter 7 Conclusion and Outlook;236
12.1;7.1 Conclusions;236
12.2;7.2 Outlook;238
13;Appendix A DAC Bias Noise Model;241
13.1;A.1 Bias Noise Model Without 1/f-Noise;241
13.2;A.2 DMT Synthesis with Correlated 1/f-Noise;243
13.3;A.3 Maximum SNR Limited by Correlated Bias Noise;246
14;Appendix B Jitter Noise;248
14.1;B.1 Sampling Jitter Model;248
14.2;B.2 Non Return-to-Zero DAC;250
14.3;B.3 Return-to-Zero DAC;252
14.4;B.4 Jitter in Multitone Systems;255
15;Appendix C Code-Dependent Output Resistance;260
15.1;C.1 Single-Ended Converter;260
15.2;C.2 Fully Differential Converter;262
16;Appendix D Switching errors;265
16.1;D.1 Generalized Switching Error Model;265
16.2;D.2 Switching Transition Mismatch with Thermometer Coding;267
16.3;D.3 Switching Transition Mismatch with Data Weighted Averaging;269
16.4;D.4 Charge Sharing with Thermometer Coding;271
16.5;D.5 Charge Sharing with Data Weighted Averaging;272
16.6;D.6 Output Voltage Feedthrough Factor;273
16.6.1;D.6.1 Single-Polarity DAC with Passive Termination;274
16.6.2;D.6.2 Dual-Polarity DAC with Active Termination;276
16.7;D.7 Third-Order Two-Tone Nonlinearity;277
17;About the Author;282
18;References;284
19;Index;293