Dongwoo / Cheng Efficient Test Methodologies for High-Speed Serial Links

1. Auflage 2009
ISBN: 978-90-481-3443-4
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Wasserzeichen (»Systemvoraussetzungen)

E-Book, Englisch, 98 Seiten

Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.

Autoren/Hrsg.

Dongwoo, Hong

Cheng, Kwang-Ting

Inhaltsverzeichnis

1;Efficient Test Methodologiesfor High-Speed Serial Links;1
1.1;1 Introduction;11
1.1.1;1.1 Overview of High-Speed Serial Links;11
1.1.1.1;1.1.1 High-Speed Serial Link System;11
1.1.1.2;1.1.2 Testing High-Speed Serial Links;12
1.1.2;1.2 Challenges in Testing High-Speed Serial Links;13
1.1.3;1.3 Contributions of the Dissertation;14
1.2;2 An Efficient Jitter Measurement Technique;16
1.2.1;2.1 Comparator Undersampling Technique;16
1.2.2;2.2 Random Jitter Measurement;18
1.2.2.1;2.2.1 Proposed RJ Measurement Technique;19
1.2.2.2;2.2.2 Limitations of the Technique;21
1.2.3;2.3 Experimental Results;22
1.2.3.1;2.3.1 Simulation Results;23
1.2.3.1.1;2.3.1.1 Simulation: Case 1;23
1.2.3.1.2;2.3.1.2 Simulation: Case 2;23
1.2.3.1.3;2.3.1.3 Simulation: Case 3;24
1.2.3.2;2.3.2 Measurement Results;25
1.2.3.2.1;2.3.2.1 Experiment: Case 1;25
1.2.3.2.2;2.3.2.2 Experiment: Case 2;26
1.2.4;2.4 Summary;27
1.3;3 BER Estimation for Linear Clock and Data Recovery Circuit;28
1.3.1;3.1 BER Analysis with Random Jitter;29
1.3.1.1;3.1.1 Error Occurrences;29
1.3.1.2;3.1.2 BER Estimation with Random Jitter;29
1.3.2;3.2 BER Analysis with Random Jitter and Periodic Jitter;31
1.3.2.1;3.2.1 Jitter Transfer Characteristics of a CDR Circuit;32
1.3.2.2;3.2.2 BER Estimation with RJ and PJ;34
1.3.2.2.1;3.2.2.1 Dual-Dirac Model and Its Modification;34
1.3.2.2.2;3.2.2.2 BER Estimation Taking into Account Clock Recovery Function;35
1.3.3;3.3 BER Analysis Including Intrinsic Noise in the CDR Circuit;41
1.3.4;3.4 Experimental Results;43
1.3.4.1;3.4.1 Simulation Results;43
1.3.4.2;3.4.2 Hardware Validation Results;44
1.3.4.2.1;3.4.2.1 Jitter Transfer Characteristics;45
1.3.4.2.2;3.4.2.2 BER Measurement Results;47
1.3.5;3.5 Summary and Future Work;49
1.4;4 BER Estimation for Non-linear Clock and Data Recovery Circuit;50
1.4.1;4.1 Jitter Analysis for BB CDR Circuits;50
1.4.1.1;4.1.1 Jitter Transfer Analysis;51
1.4.1.2;4.1.2 Jitter Tolerance Analysis;54
1.4.2;4.2 BER Estimation;54
1.4.2.1;4.2.1 Variation of Jitter Transfer Due to RJ;55
1.4.2.2;4.2.2 BER Estimation;57
1.4.3;4.3 Experimental Setup and Results;58
1.4.3.1;4.3.1 Simulation Setup;58
1.4.3.2;4.3.2 Simulation Results;59
1.4.4;4.4 Summary;60
1.5;5 Gaps in Timing Margining Test;61
1.5.1;5.1 Timing Margining Test Basics;61
1.5.2;5.2 Gap Analysis in Timing Margining Test;62
1.5.2.1;5.2.1 Random Jitter;63
1.5.2.2;5.2.2 PLL-Based Clock Recovery with Non-linear Phase Detector;64
1.5.2.3;5.2.3 Jitter Amplification;67
1.5.2.4;5.2.4 Duty Cycle Distortion in Clock;69
1.5.3;5.3 Summary and Future Work;71
1.6;6 An Accurate Jitter Estimation Technique;73
1.6.1;6.1 Characteristics of DJ;73
1.6.1.1;6.1.1 ISI-Induced Jitter;74
1.6.1.2;6.1.2 Crosstalk-Induced Jitter;74
1.6.2;6.2 Total Jitter Estimation;76
1.6.2.1;6.2.1 Estimation Based on Dual-Dirac Model;76
1.6.2.2;6.2.2 High-Order Polynomial Fitting;79
1.6.2.3;6.2.3 Accuracy Versus Number of Samples for Fitting;79
1.6.3;6.3 Summary;80
1.7;7 A Two-Tone Test Method for Continuous-Time Adaptive Equalizers;82
1.7.1;7.1 Continuous-Time Adaptive Equalizer;83
1.7.2;7.2 Proposed Two-Tone Test Method;85
1.7.2.1;7.2.1 Description of the Test Method;85
1.7.2.2;7.2.2 Implementation of the Test Method;86
1.7.3;7.3 Experimental Results;89
1.7.3.1;7.3.1 MATLAB Simulation Results;89
1.7.3.2;7.3.2 Transistor-Level Simulation Results;91
1.7.4;7.4 Summary and Future Work;92
1.8;8 Conclusions;95
1.9;A Extracting Effective PJ and RJ Components from Jitter Histogram;97
1.10;References;100