Flynn / Aitken / Gibbons Low Power Methodology Manual

For System-on-Chip Design
1. Auflage 2007
ISBN: 978-0-387-71819-4
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 300 Seiten

Reihe: Integrated Circuits and Systems

This book provides a practical guide for engineers doing low power System-on-Chip (SoC) designs. It covers various aspects of low power design from architectural issues and design techniques to circuit design of power gating switches. In addition to providing a theoretical basis for these techniques, the book addresses the practical issues of implementing them in today's designs with today's tools.

ABOUT THE AUTHORS: Michael Keating is a Synopsys Fellow in the company's Advanced Technology Group, focusing on IP development methodology, hardware and software design quality and low power design. David Flynn is an ARM R&D Fellow and has been with the company since 1991, specializing in low power System-on-Chip IP deployment and methodology. Robert Aitken is an ARM R&D Fellow. His areas of responsibility include memory architecture, design for testability and design for manufacturability. Alan Gibbons is a Principal Engineer at Synopsys, with a focus on development of advanced methodology and technology for ARM processor-based system design. Kaijian Shi is a Principal Consultant in the Professional Services Group of Synopsys, specializing in low power design methodology and implementation.

Autoren/Hrsg.

Flynn, David

Aitken, Rob

Gibbons, Alan

Shi, Kaijian

Inhaltsverzeichnis

1;Preface;6
2;Table of Contents;8
3;1 Introduction;15
3.1;1.1 Overview;15
3.2;1.2 Scope of the Problem;16
3.3;1.3 Power vs. Energy;17
3.4;1.4 Dynamic Power;18
3.5;1.5 The Conflict Between Dynamic and Static Power;21
3.6;1.6 Static Power;22
3.7;1.7 Purpose of This Book;24
4;2 Standard Low Power Methods;27
4.1;2.1 Clock Gating;27
4.2;2.2 Gate Level Power Optimization;29
4.3;2.3 Multi VDD;30
4.4;2.4 Multi-Threshold Logic;31
4.5;2.5 Summary of the Impact of Standard Low Power Techniques;33
5;3 Multi- Voltage Design;34
5.1;3.1 Challenges in Multi-Voltage Designs;35
5.2;3.2 Voltage Scaling Interfaces – Level Shifters;35
5.3;3.3 Timing Issues in Multi-Voltage Designs;42
5.4;3.4 Power Planning for Multi-Voltage Design;43
5.5;3.5 System Design Issues with Multi-Voltage Designs;44
6;4 Power Gating Overview;45
6.1;4.1 Dynamic and Leakage Power Profiles;45
6.2;4.2 Impact of Power Gating on Classes of Sub-Systems;48
6.3;4.3 Principles of Power Gating Design;49
7;5 Designing Power Gating;53
7.1;5.1 Switching Fabric Design;54
7.2;5.2 Signal Isolation;57
7.3;5.3 State Retention and Restoration Methods;62
7.4;5.4 Power Gating Control;71
7.5;5.5 Power Gating Design Verification – RTL Simulation;75
7.6;5.6 Design For Test Considerations;82
7.7;6.1 Hierarchy and Power Gating;86
8;6 Architectural Issues for Power Gating ;86
8.1;6.2 Power Networks and Their Control;89
8.2;6.3 Power State Tables and Always On Regions;93
9;7 A Power Gating Example;95
9.1;7.1 Leakage Modes Supported;95
9.2;7.2 Design Partitioning;98
9.3;7.3 Isolation;102
9.4;7.4 Retention;104
9.5;7.5 Inferring Power Gating and Retention;105
9.6;7.6 Measurements and Analysis;106
10;8 IP Design for Low Power;111
10.1;8.1 Architecture and Partitioning for Power Gating;112
10.2;8.2 Power Controller Design for the USB OTG;115
10.3;8.3 Issues in Designing Portable Power Controllers;118
10.4;8.4 Clocks and Resets;119
10.5;8.5 Verification;119
10.6;8.6 Packaging IP for Reuse with Power Intent;120
10.7;8.7 UPF for the USB OTG Core;121
10.8;8.8 USB OTG Power Gating Controller State Machine;124
11;9 Frequency and Voltage Scaling Design;130
11.1;9.1 Dynamic Power and Energy;131
11.2;9.2 Voltage Scaling Approaches;134
11.3;9.3 Dynamic Voltage and Frequency Scaling (DVFS);134
11.4;9.4 CPU Subsystem Design Issues;138
11.5;9.5 Adaptive Voltage Scaling (AVS);139
11.6;9.6 Level Shifters and Isolation;140
11.7;9.7 Voltage Scaling Interfaces – Effect on Synchronous Timing;141
11.8;9.8 Control of Voltage Scaling;145
12;10 Examples of Voltage Design and Frequency Scaling Examples of Voltage;147
12.1;10.1 Voltage Scaling - A Worked Example for UMC 130nm;147
12.2;10.2 65nm Voltage Scaling – A Worked Example for TSMC;158
13;11 Implementing Multi- Voltage, Power Gated Designs;163
13.1;11.1 Design Partitioning;166
13.2;11.2 Design Flow Overview;168
13.3;11.3 Synthesis;170
13.4;11.4 Multi Corner Multi Mode Optimization with Voltage Scaling Designs;179
13.5;11.5 Design Planning;181
13.6;11.6 Power Planning;185
13.7;11.7 Clock Tree Synthesis;188
13.8;11.8 Power Analysis;191
13.9;11.9 Timing Analysis;192
13.10;11.10Low Power Validation;193
13.11;11.11 Manufacturing Test;193
14;12 Physical Libraries;195
14.1;12.1 Standard Cell Libraries;195
14.2;12.2 Special Cells - Isolation Cells;198
14.3;12.3 Special Cells - Level Shifters;203
14.4;12.4 Memories;206
14.5;12.5 Power Gating Strategies and Structures;208
14.6;12.6 Power Gating Cells;212
14.7;12.7 Power Gated Standard Cell Libraries;214
15;13 Retention Register Design;216
15.1;13.1 Retention Registers;216
15.2;13.2 Memory Retention Methods;226
16;14 Design of the Power Switching Network;231
16.1;14.1 Ring vs. Grid Style;231
16.2;14.2 Header vs. Footer Switch;238
16.3;14.3 Rail vs. Strap VDD Supply;242
16.4;14.4 A Sleep Transistor Example;245
16.5;14.5 Wakeup Current and Latency Control Methods;246
16.6;14.6 An Example of a Dual Daisy Chain Sleep Transistor Implementation;252
17;A Sleep Transistor Design;254
17.1;A.1 Sleep Transistor Design Metrics;255
17.2;PMOS Vth (Vdd=1, T=30, Vbb=0..1V);260
17.3;Vth ( V);260
17.4;A.2 Layout Design for Area Efficiency;265
17.5;A.3 Single Row vs. Double Row;267
17.6;A.4 In-rush Current and Latency Analysis;268
18;B UPF Command Syntax;271
18.1;B.1 add_pst_state;272
18.2;B.2 connect_supply_net;273
18.3;B.3 create_power_domain;275
18.4;B.4 create_power_switch;277
18.5;B.5 create_pst;279
18.6;B.6 create_supply_net;280
18.7;B.7 create_supply_port;281
18.8;B.8 set_domain_supply_net;282
18.9;B.9 set_isolation;283
18.10;B.10 set_isolation_control;285
18.11;B.11 set_level_shifter;287
18.12;B.12 set_retention;289
18.13;B.13 set_retention_control;291
18.14;B.14 set_scope;292
19;Glossary;294
20;Bibliography;296
21;Index;300