Hübner / Becker Multiprocessor System-on-Chip

Hardware Design and Tool Integration
1. Auflage 2010
ISBN: 978-1-4419-6460-1
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 270 Seiten

The purpose of this book is to evaluate strategies for future system design in multiprocessor system-on-chip (MPSoC) architectures. Both hardware design and integration of new development tools will be discussed. Novel trends in MPSoC design, combined with reconfigurable architectures are a main topic of concern. The main emphasis is on architectures, design-flow, tool-development, applications and system design.

Autoren/Hrsg.

Hübner, Michael

Becker, Jürgen

Inhaltsverzeichnis

1;Preface;6
2;Contents;8
3;Chapter 1: An Introduction to Multi-Core System on Chip - Trends and Challenges;10
3.1;1.1 From SoC to MPSoC;10
3.2;1.2 General Structure of MPSoC;11
3.2.1;1.2.1 Processing Elements;11
3.2.2;1.2.2 Interconnection;12
3.2.3;1.2.3 Power Management;12
3.3;1.3 Power Efficiency and Adaptability;13
3.4;1.4 Complexity and Scalability;15
3.5;1.5 Heterogeneous and Homogeneous Approaches;16
3.5.1;1.5.1 Heterogeneous MPSoC;16
3.5.2;1.5.2 Homogeneous MPSoC;17
3.6;1.6 Multi variable Optimization;20
3.6.1;1.6.1 Static Optimization;20
3.6.2;1.6.2 Dynamic Optimization;20
3.6.2.1;1.6.2.1 Centralized Approaches;21
3.6.2.2;1.6.2.2 Distributed Approaches;24
3.7;1.7 Static vs Dynamic Centralized and Distributed Approaches;25
3.8;1.8 Conclusion;27
3.9;References;28
4;Part I: ``Application Mapping and Communication Infrastructure´´;31
4.1;Chapter 2: Composability and Predictability for Independent Application Development,Verification, and Execution;32
4.1.1;2.1 Introduction;32
4.1.2;2.2 Composability and Predictability;34
4.1.2.1;2.2.1 Terminology;34
4.1.2.2;2.2.2 Composable Resources;38
4.1.2.3;2.2.3 Predictable resources;41
4.1.2.4;2.2.4 Composable and predictable resources;42
4.1.3;2.3 Processor tile;45
4.1.3.1;2.3.1 Composability;45
4.1.3.1.1;2.3.1.1 Constant task slots;46
4.1.3.1.2;2.3.1.2 Constant OS slot;47
4.1.3.1.3;2.3.1.3 Two-level application and task scheduling;48
4.1.3.2;2.3.2 Predictability;48
4.1.4;2.4 Interconnect;49
4.1.4.1;2.4.1 Composability;50
4.1.4.2;2.4.2 Predictability;51
4.1.5;2.5 Memory tile;51
4.1.5.1;2.5.1 Predictability;52
4.1.5.1.1;2.5.1.1 Predictable SDRAM back-end;52
4.1.5.1.2;2.5.1.2 Predictable arbitration;55
4.1.5.2;2.5.2 Composability;56
4.1.6;2.6 Experiments;57
4.1.7;2.7 Conclusions;59
4.1.8;References;61
4.2;Chapter 3: Hardware Support for Efficient Resource Utilization in Manycore Processor Systems;64
4.2.1;3.1 Introduction;65
4.2.2;3.2 Learning from Network Processing Applications;67
4.2.2.1;3.2.1 Commercial Network Processors;68
4.2.2.2;3.2.2 Example Networking Applications;69
4.2.2.3;3.2.3 The FlexPath NP Approach;70
4.2.2.4;3.2.4 What Can Other Manycore Domains Learn from Network Processing?;75
4.2.3;3.3 Learning from HPC and Scientific Computing;77
4.2.3.1;3.3.1 Hierarchical Multi-Topology Networks-on-Chip;77
4.2.3.2;3.3.2 Task Management;81
4.2.3.3;3.3.3 Synchronization Subsystem;82
4.2.3.4;3.3.4 What Can Other Manycore Domains Learn from Supercomputing?;83
4.2.4;3.4 Learning from Bio-Inspired, Self-Organizing Systems in Nature;84
4.2.4.1;3.4.1 Collective Behavior of Entities in Natural and Technical Systems;84
4.2.4.2;3.4.2 Technical Realization of Self-Adaptive IP Cores;86
4.2.4.3;3.4.3 What Can Manycore Domains Learn from Nature?;90
4.2.5;3.5 Summary and Conclusions;92
4.2.6;References;93
4.3;Chapter 4: PALLAS: Mapping Applications onto Manycore;95
4.3.1;4.1 PALLAS;96
4.3.2;4.2 Driving Applications;97
4.3.2.1;4.2.1 Content-Based Image Retrieval;97
4.3.2.2;4.2.2 Optical Flow and Tracking;99
4.3.2.3;4.2.3 Stationary Video Background Subtraction;101
4.3.2.4;4.2.4 Automatic Speech Recognition;102
4.3.2.5;4.2.5 Compressed Sensing MRI;103
4.3.2.6;4.2.6 Market Value-at-Risk Estimation in Computational Finance;105
4.3.2.7;4.2.7 Games;106
4.3.2.8;4.2.8 Machine Translation;107
4.3.2.9;4.2.9 Summary;108
4.3.3;4.3 Perspectives on Parallel Performance;109
4.3.3.1;4.3.1 Linear Scaling Not Required;109
4.3.3.2;4.3.2 Measure Real Problems on Real Hardware;110
4.3.3.3;4.3.3 Consider the Algorithms;110
4.3.3.4;4.3.4 Summing Up;111
4.3.4;4.4 Patterns to Frameworks;111
4.3.4.1;4.4.1 Application Frameworks;112
4.3.4.2;4.4.2 Programming Frameworks;114
4.3.4.2.1;4.4.2.1 Efficiency and Portability Through Programming Frameworks;114
4.3.4.2.2;4.4.2.2 Copperhead;115
4.3.5;4.5 Conclusions;116
4.3.6;4.6 Appendices;117
4.3.6.1;4.6.1 Structural Patterns;117
4.3.6.2;4.6.2 Computational Patterns;117
4.3.6.3;4.6.3 Parallel Algorithm Strategy Patterns;118
4.3.7;References;118
4.4;Chapter 5: The Case for Message Passing on Many-Core Chips;120
4.4.1;5.1 Metrics for Comparing Parallel Programming Models;121
4.4.2;5.2 Comparison Framework;122
4.4.3;5.3 Comparing Message Passing and Shared Memory;123
4.4.3.1;5.3.1 Agenda Parallelism;123
4.4.3.2;5.3.2 Result Parallelism;124
4.4.3.3;5.3.3 Specialist Parallelism;125
4.4.4;5.4 Architectural Implications;126
4.4.5;5.5 Discussion and Conclusion;127
4.4.6;References;128
5;Part II: ``Reconfigurable Hardware in Multiprocessor Systems´´;129
5.1;Chapter 6: Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support;130
5.1.1;6.1 Introduction;131
5.1.2;6.2 Background: Introduction to Reconfigurable Hardware;133
5.1.2.1;6.2.1 Basic Concept of Runtime Reconfiguration;133
5.1.2.2;6.2.2 Basic Concept of Runtime Reconfiguration and Classification of Configurable Granularity;135
5.1.3;6.3 Related Work;138
5.1.4;6.4 The RAMPSoC Approach;139
5.1.5;6.5 Hardware Architecture of RAMPSoC;142
5.1.6;6.6 Design Methodology of RAMPSoC;144
5.1.7;6.7 CAP-OS: Configuration Access Port-Operating System for RAMPSoC;148
5.1.8;6.8 Conclusions and Outlook;152
5.1.9;References;152
6;Part III: ``Physical Design of Multiprocessor Systems´´;155
6.1;Chapter 7: Design Tools and Methods for Chip Physical Design;156
6.1.1;7.1 Introduction;157
6.1.2;7.2 Use of MOS Complex Gates;158
6.1.3;7.3 Wirelength Reduction;159
6.1.4;7.4 Power Reduction;159
6.1.5;7.5 Layout Strategies;159
6.1.6;7.6 Layout as a Network of Transistors;161
6.1.7;7.7 Using ASTRAN to Help in the Synthesis of Analog Modules;163
6.1.8;7.8 Conclusions;166
6.1.9;References;166
6.2;Chapter 8: Power-Aware Multicore SoC and NoC Design;168
6.2.1;8.1 Introduction;168
6.2.2;8.2 Power Estimation Models: From Spreadsheets to Power State Machines;172
6.2.2.1;8.2.1 Power Models of Processors;174
6.2.2.2;8.2.2 Power Models of Memory;175
6.2.2.3;8.2.3 Power Models of On-Chip Interconnects;176
6.2.2.4;8.2.4 Power Models for Embedded Software;178
6.2.2.5;8.2.5 Power Estimation, Analysis, and Optimization Tools;180
6.2.2.6;8.2.6 Standardization and Power Formats;182
6.2.3;8.3 Power Management;183
6.2.3.1;8.3.1 Categorization of Management Techniques;185
6.2.3.2;8.3.2 Dynamic Monitoring for Power and Thermal Management;185
6.2.4;8.4 Future Trends;189
6.2.5;References;190
7;Part IV: Trends and Challenges for Multiprocessor Systems;195
7.1;Chapter 9: Embedded Multicore Systems: Design Challenges and Opportunities;196
7.1.1;9.1 Introduction;196
7.1.2;9.2 ``Real World´´ Requirements;197
7.1.2.1;9.2.1 Continuing Demand for Higher Performance at Constant Power Envelope;197
7.1.2.2;9.2.2 Demand for Higher System Integration;198
7.1.3;9.3 Industry Growth Drivers and Sustainable Megatrends;199
7.1.3.1;9.3.1 Interactive World;199
7.1.3.2;9.3.2 Connected World;200
7.1.3.3;9.3.3 Safer World;200
7.1.4;9.4 Distinguishing Multicore SoC Features;200
7.1.4.1;9.4.1 Virtualization;202
7.1.4.2;9.4.2 Heterogeneous Multicore System;203
7.1.5;9.5 Multicore Design: Key Considerations;204
7.1.6;9.6 Performance;205
7.1.7;9.7 System Bandwidth;205
7.1.8;9.8 Software Complexity;206
7.1.9;9.9 SoC Integration;206
7.1.9.1;9.9.1 Area and Power;207
7.1.9.2;9.9.2 The Critical Role of Interconnect;208
7.1.9.3;9.9.3 Choice of Interconnection Topologies;209
7.1.9.4;9.9.4 Software;210
7.1.9.5;9.9.5 Heterogeneous Manycore;211
7.1.10;9.10 Multicore Design: Challenges and Opportunities;212
7.1.10.1;9.10.1 Meeting Performance Goals;212
7.1.10.2;9.10.2 Standards-Based Programming Models;215
7.1.10.3;9.10.3 Advanced Debugging and Optimization;218
7.1.11;9.11 Conclusions;219
7.1.12;References;220
7.2;Chapter 10: High-Performance Multiprocessor System on Chip: Trends in Chip Architecture for the Mass Market;222
7.2.1;10.1 Introduction;222
7.2.1.1;10.1.1 Mass Markets and High Performance;222
7.2.2;10.2 Scaling and Consumer Expectations;224
7.2.2.1;10.2.1 Scaling Limitations;225
7.2.3;10.3 CPU Trends;227
7.2.3.1;10.3.1 Power;228
7.2.3.2;10.3.2 Dark Silicon;229
7.2.3.3;10.3.3 What to do with Dark Silicon;232
7.2.4;10.4 Conclusion;237
7.2.5;References;238
7.3;Chapter 11: Invasive Computing: An Overview;239
7.3.1;11.1 Introduction;240
7.3.1.1;11.1.1 Parallel Processing Has Become Mainstream;240
7.3.1.2;11.1.2 Obstacles and Pitfalls in the Years 2020 and Beyond;242
7.3.1.3;11.1.3 Principles and Challenges of Invasive Computing;244
7.3.1.4;11.1.4 Architectural Challenges for the Support of Invasive Computing;245
7.3.1.5;11.1.5 Notational Issues for the Support of Invasive Computing;251
7.3.1.6;11.1.6 Algorithmic and Language Challenges for the Support of Invasive Computing;252
7.3.1.7;11.1.7 Operating System Issues of Invasive Computing;256
7.3.2;11.2 Examples of Invasive Programs;257
7.3.3;11.3 Expected Impact and Risks;263
7.3.4;References;238
8;Index;267