Kumar / Corporaal / Mesman Multimedia Multiprocessor Systems

Analysis, Design and Management
1. Auflage 2010
ISBN: 978-94-007-0083-3
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 164 Seiten

Reihe: Embedded Systems

Modern multimedia systems are becoming increasingly multiprocessor and heterogeneous to match the high performance and low power demands placed on them by the large number of applications. The concurrent execution of these applications causes interference and unpredictability in the performance of these systems. In Multimedia Multiprocessor Systems, an analysis mechanism is presented to accurately predict the performance of multiple applications executing concurrently. With high consumer demand the time-to-market has become significantly lower. To cope with the complexity in designing such systems, an automated design-flow is needed that can generate systems from a high-level architectural description such that they are not error-prone and consume less time. Such a design methodology is presented for multiple use-cases -- combinations of active applications. A resource manager is also presented to manage the various resources in the system, and to achieve the goals of performance prediction, admission control and budget enforcement.

Akash Kumar was born in Bijnor, India on November 13, 1980. After finishing the middle high-school at the Dayawati Modi Academy in Rampur, India in 1996, he proceeded to Raffles Junior College, Singapore for his pre-university education. In 2002, he completed Bachelors in Computer Engineering (First Class Honours) from the National University of Singapore (NUS), and in 2004 he completed joint Masters in Technological Design (Embedded Systems) from Eindhoven University of Technology (TUe) and NUS. In 2005, he began working towards his joint Ph.D. degree from TUe and NUS in the Electronic Systems group and Electical and Computer Engineering department respectively. His research was funded by STW within the PreMaDoNA project. It has led, among others, to several publications and this book. Presently, Akash is a visiting fellow at the Department of Electrical and Computer Engineering, NUS, Singapore. His research interests include analysis, design methodologies, and resource management of multi-processor systems. Henk Corporaal has gained a MSc in Theoretical Physics from the University of Groningen, and a PhD in Electrical Engineering, in the area of Computer Architecture, from Delft University of Technology. Corporaal has been teaching at several schools for higher education, has been associate professor at the Delft University of Technology in the field of computer architecture and code generation, had a joint professor appointment at the National University of Singapore, and has been scientific director of the joined NUS-TUE Design Technology Institute. He also has been department head and chief scientist within the DESICS (Design Technology for Integrated Information and Communication Systems) division at IMEC, Leuven (Belgium). Currently Corporaal is Professor in Embedded System Architectures at the Einhoven University of Technology (TU/e) in The Netherlands. He has co-authored over 250 journal and conference papers in the (multi-)processor architecture and embedded system design area. Furthermore he invented a new class of VLIW architectures, the Transport Triggered Architectures, which is used in several commercial products, and by many research groups. His current research projects are on the predictable design of soft- and hard real-time embedded systems. Bart Mesman obtained his Ph.D. from the Eindhoven University of Technology in 2001. His thesis discusses an efficient constraint-satisfaction method for scheduling operations on a distributed VLIW processor architecture with highly constrained register files with stringent timing requirements. He has worked at Philips Research from 1995-2005 on DSP processor architectures and compilation. Dr. Mesman is currently employed by Eindhoven University. His research interests include (multi-)processor architectures, compile-time and run-time scheduling, and resource management in multi-media devices. Yajun Ha received the BS degree in Electrical Engineering from Zhejiang University, Hangzhou, China, in 1996, the MEng degree in Electrical Engineering from the National University of Singapore (NUS), Singapore, in 1999, and the PhD degree in Electrical Engineering from Katholieke Universiteit Leuven, Leuven, Belgium, in 2004. He has been an assistant professor at the Department of Electrical and Computer Engineering, NUS, since 2004. Between 1999 and 2004, he did his PhD research project at IMEC, Leuven. His research interests lie in the embedded system architecture and design methodologies, particularly in the area of reconfigurable computing. He has held a US patent and published more than 50 internationally refereed technical papers in his interested areas.

Autoren/Hrsg.

Kumar, Akash

Corporaal, Henk

Mesman, Bart

Ha, Yajun

Inhaltsverzeichnis

1;Preface;5
1.1;Preface and Outline;5
1.2;Aim of This Book;6
1.3;Audience;7
1.4;Accompanying Material;8
1.5;Organization of This Book;8
2;Contents;9
3;List of Figures;11
4;List of Tables;15
5;Trends and Challenges in Multimedia Systems;17
5.1;Trends in Multimedia Systems Applications;19
5.2;Trends in Multimedia Systems Design;20
5.3;Key Challenges in Multimedia Systems Design;26
5.3.1;Analysis;27
5.3.2;Design;29
5.3.3;Management;30
5.4;Design Flow;31
5.5;Book Overview;33
6;Application Modeling and Scheduling;34
6.1;Application Model and Specification;35
6.2;Introduction to SDF Graphs;37
6.2.1;Modeling Auto-concurrency;38
6.2.2;Modeling Buffer Sizes;39
6.3;Comparison of Dataflow Models;40
6.3.1;Kahn Process Network;41
6.3.2;Scenario Aware Dataflow;41
6.3.3;Boolean Dataflow;42
6.3.4;Cyclo Static Dataflow;42
6.3.5;Computation Graphs;42
6.3.6;Synchronous Dataflow;43
6.3.7;Homogeneous Synchronous Dataflow;43
6.4;Performance Modeling;43
6.4.1;Steady-State vs Transient Behaviour;44
6.4.2;Throughput Analysis of (H)SDF Graphs;46
6.5;Scheduling Techniques for Dataflow Graphs;47
6.6;Analyzing Application Performance on Hardware;49
6.6.1;Static Order Analysis;49
6.6.2;Deadlock Analysis;53
6.6.3;Dynamic Order Analysis;54
6.7;Composability;56
6.7.1;Performance Estimation;57
6.8;Static vs Dynamic Ordering;60
6.9;Conclusions;61
7;Probabilistic Performance Prediction;63
7.1;Basic Probabilistic Analysis;66
7.1.1;Generalizing the Analysis;67
7.1.2;Extending to N Actors;69
7.1.3;Reducing Complexity;72
7.1.3.1;Composability-Based Approach;73
7.1.3.2;Computing Inverse of Formulae;74
7.2;Iterative Analysis;75
7.2.1;Terminating Condition;80
7.2.2;Conservative Iterative Analysis;81
7.2.3;Parametric Throughput Analysis;82
7.2.4;Intra-task Dependencies;82
7.2.5;Handling Other Arbiters;83
7.3;Experiments;83
7.3.1;Setup;84
7.3.2;Results and Discussion - Basic Analysis;84
7.3.3;Results and Discussion - Iterative Analysis;86
7.3.3.1;Validating the Probabilistic Distribution;86
7.3.3.2;Application Throughput;90
7.3.4;Varying Execution Times;93
7.3.5;Mapping Multiple Actors;94
7.3.6;Mobile Phone Case Study;94
7.3.7;Comparison with an FPGA Multiprocessor Implementation;96
7.3.8;Implementation Results on an Embedded Processor;98
7.4;Suggested Readings;99
7.5;Conclusions;100
8;Resource Management;101
8.1;Off-line Derivation of Properties;102
8.1.1;Performance Specification;104
8.2;On-line Resource Manager;105
8.2.1;Admission Control;106
8.2.1.1;Performance Predictor;106
8.2.1.2;Resource Assignment;107
8.2.1.3;Task Migration;108
8.2.2;Resource Budget Enforcement;108
8.2.2.1;Motivating Example;109
8.2.2.2;Suspending Applications;110
8.2.2.3;Suspension Example;110
8.2.2.4;Communication Overhead;111
8.2.2.5;Arbiter vs Resource Manager;112
8.3;Achieving Predictability Through Suspension;113
8.3.1;Reducing Complexity;115
8.3.2;Dynamism vs Predictability;116
8.4;Experiments;116
8.4.1;DSE Case Study;116
8.4.2;Predictability Through Suspension;119
8.5;Suggested Readings;121
8.6;Conclusions;123
9;Multiprocessor System Design and Synthesis;125
9.1;Performance Evaluation Framework;127
9.2;MAMPS Flow Overview;128
9.2.1;Application Specification;129
9.2.2;Functional Specification;130
9.2.3;Platform Generation;130
9.3;Tool Implementation;132
9.3.1;Resource Manager;133
9.4;Experiments and Results;133
9.4.1;Reducing the Implementation Gap;134
9.4.2;DSE Case Study;137
9.4.2.1;Design Time;138
9.5;Suggested Readings;139
9.6;Conclusions;141
10;Multiple Use-cases System Design;142
10.1;Merging Multiple Use-cases;143
10.1.1;Generating Hardware for Multiple Use-cases;144
10.1.2;Generating Software for Multiple Use-cases;145
10.1.3;Combining the Two Flows;146
10.2;Use-case Partitioning;147
10.2.1;Hitting the Complexity Wall;149
10.2.2;Reducing the Execution Time;149
10.2.3;Reducing Complexity;150
10.3;Estimating Area: Does It Fit?;151
10.3.1;Packing the Most;153
10.4;Experiments and Results;154
10.4.1;Use-case Partitioning;154
10.4.2;Mobile-Phone Case Study;155
10.4.2.1;Reconfiguration Time;156
10.5;Suggested Readings;156
10.6;Conclusions;157
11;Conclusions and Open Problems;158
11.1;Conclusions;158
11.2;Open Problems;160
12;About the Authors;163
13;Glossary;165
14;References;167
15;Index;173