Lau Fan-Out Wafer-Level Packaging

1. Auflage 2018
ISBN: 978-981-10-8884-1
Verlag: Springer Nature Singapore
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 319 Seiten

This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semiconductor Manufacturing Company (TSMC) employed their InFO (integrated fan-out) technology in A10, the application processor for Apple's iPhone, in 2016, generating great excitement about FOWLP technology throughout the semiconductor packaging community. For many practicing engineers and managers, as well as scientists and researchers, essential details of FOWLP - such as the temporary bonding and de-bonding of the carrier on a reconstituted wafer/panel, epoxy molding compound (EMC) dispensing, compression molding, Cu revealing, RDL fabrication, solder ball mounting, etc. - are not well understood.  Intended to help readers learn the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions quickly, this book serves as a valuable reference guide for all those faced with the challenging problems created by the ever-increasing interest in FOWLP, helps to remove roadblocks, and accelerates the design, materials, process, and manufacturing development of key enabling technologies for FOWLP.

SPECIALIZED PROFESSIONAL COMPETENCE
Design, analysis, materials, process, manufacturing, qualification, reliability, testing, and thermal management of electronic and optoelectronic components and systems. SMT, fan-out/fan-in WLP, TSV, 3D IC Integration, heterogeneous integration and SiP. Leadfree soldering, manufacturing, and solder joint reliability. Management of a R&D Laboratory and Company. BACKGROUND AND PROFESSIONAL EXPERIENCE Ph.D.  (Theoretical and Applied Mechanics), University of Illinois, Urbana, IL (1977) M.S.   (Engineering Physics), University of Wisconsin, Madison, WI (1974) M.S.   (Structural Mechanics), University of British Columbia, Vancouver, BC (1973) M.S.   (Management Science), Fairleigh Dickinson University, Teaneck, NJ (1981) B.S.   (Civil Engineering), National Taiwan University, Taipei, Taiwan (1970)   ASM Pacific Technology (Sr. Technical Advisor), Hong Kong, July 2014 - Present Industrial Technology Research Institute (ITRI Fellow), Taiwan, Jan 2010 - June 2014 Hong Kong University of Science & Technology (Visiting Professor), Jan 2009 - Jan 2010 Institute of Microelectronic, (Director, System Packaging Lab), Singapore, 2006 - Jan 2009 Agilent Technologies, Inc. (Sr. Interconnection Specialist), Santa Clara, CA, 2000-2006 Express Packaging Systems, Inc., (President), Palo Alto, CA, 1995-2000 Hewlett-Packard Labs/Company (Senior MTS/Individual Contributor), Palo Alto, CA, 1984-1995 Sandia National Laboratories (Member of Technical Staff), Albuquerque, NM, 1982-1983 Bechtel Power Corporation (Lead Engineer), San Francisco, CA, 1981-1982 Ebasco (Lead Engineer), New York, NY, 1978-1980 Exxon Production and Research Company (Research Engineer), Houston, TX, 1977-1978   Editorial Board of ASME Transactions, Journal of Electronic Packaging, 1989-1999 Editorial Board of IEEE Transactions on Components, Packaging, Manufacture Technology, 1990-1995 Editor-in-Chief, Circuit World, 1998-2000. Program Chair ('90) to General Chair ('92) of the IEEE/CPMT IEMTS Program Chair ('93) to General Chair ('95) of the IEEE/CPMT ECTC Publication Chair for IEEE/ECTC Symposium Organizer/Chair of the ASME Winter Annual Meeting, 1987-2002 ASME Distinguish Lecturer (2000-2003), IEEE/CPMT Distinguish Lecturer (1998-present)   ASME Worcester Reed Warner Medal (2015) IEEE Components Packaging and Manufacturing Technology Field Award (2013) IMAPS William Ashman Achievement Award (2013) Pan Wen Yuan Distinguished Research Award (2011) IEEE/CPMT Outstanding Sustained Technical Contribution Award (2010) Best IEEE Transactions Paper Award (2010 Components Packaging and Manufacturing Technology) Outstanding Paper Award (2009 IEEE EPTC) SME Total Excellence in Electronics Manufacturing Award (2001) Best ASME Transactions Paper Award (2000 Journal of Electronic Packaging) IEEE/CPMT Outstanding Contribution Awards (2000) IEEE Meritorious Achievement Award in Continuing Education (2000)    ASME/EEP Technical Achievement Award (1998) IEEE/CPMT Manufacturing Awards (1994) Best of Conference Paper Award (1989 IEEE ECTC) IEEE Fellow (since 1994), ASME Fellow (since 1999), IMAPS Fellow (since 2013) Over 20 books, 450 peer-reviewed papers, 30 issued and pending patents, and 290 keynotes/lectures.

Autoren/Hrsg.

Lau, John H.

Inhaltsverzeichnis

1;Preface;5
2;Acknowledgements;8
3;Contents;10
4;About the Author;18
5;1 Patent Issues of Fan-Out Wafer-Level Packaging;20
5.1;1.1 Introduction;20
5.2;1.2 Functions of Semiconductor Packaging;20
5.3;1.3 Level of Semiconductor Packaging;21
5.4;1.4 Patents Impacting the Semiconductor Packaging;21
5.4.1;1.4.1 Leadframe;22
5.4.2;1.4.2 Organic Substrate with Solder Balls;23
5.4.3;1.4.3 Fan-In Wafer-Level Packaging;24
5.4.4;1.4.4 Fan-Out Wafer-Level Packaging;26
5.5;1.5 Major Claims of Infineon’s Patent;29
5.6;1.6 TSMC InFO-WLP;31
5.7;1.7 Fraunhofer IZM FOPLP;34
5.8;1.8 Ball/Bump Pitch/Size of PBGA, fcPBGA, WLCSP, and FOWLP;34
5.9;1.9 Summary and Recommendations;36
5.10;References;37
6;2 Flip Chip Technology Versus FOWLP;40
6.1;2.1 Introduction;40
6.2;2.2 Wafer Bumping;43
6.2.1;2.2.1 C4 Bumps;43
6.2.2;2.2.2 C2 (Cu Pillar with Solder Cap) Bumps;44
6.3;2.3 Flip Chip Package Substrates;46
6.3.1;2.3.1 Surface Laminar Circuit (SLC) Technology;46
6.3.2;2.3.2 Integrated Thin-Film High-Density Organic Package (i-THOP);47
6.3.3;2.3.3 Coreless Substrate;49
6.3.4;2.3.4 Bump-on-Lead (BOL);50
6.3.5;2.3.5 Embedded Trace Substrate (ETS);51
6.4;2.4 Flip Chip Assembly;53
6.4.1;2.4.1 Cu-to-Cu TCB Direct Bonding;53
6.4.2;2.4.2 C4 Solder Mass Reflow;54
6.4.3;2.4.3 C2 Solder Mass Reflow;55
6.4.4;2.4.4 C2 TCB;55
6.4.4.1;2.4.4.1 C2 TCB with Low Bonding Force;56
6.4.4.2;2.4.4.2 C2 TCB with High Bonding Force;56
6.5;2.5 Underfill/Reliability;56
6.6;2.6 Post-assembly Underfill;57
6.6.1;2.6.1 Capillary Underfill (CUF);57
6.6.2;2.6.2 Molded Underfill (MUF);57
6.6.3;2.6.3 Printed Underfill;58
6.6.3.1;2.6.3.1 A New Stencil Design;59
6.6.3.2;2.6.3.2 Test Chip;60
6.6.3.3;2.6.3.3 Test Substrates;61
6.6.3.4;2.6.3.4 Flip Chip Assemblies;63
6.6.3.5;2.6.3.5 Stencil Designs;65
6.6.3.6;2.6.3.6 Test Matrix;65
6.6.3.7;2.6.3.7 Baking Substrates;66
6.6.3.8;2.6.3.8 Printing Process;67
6.6.3.9;2.6.3.9 Capillary Action and Curing;67
6.6.3.10;2.6.3.10 Effects of Underfill Viscosity, Thermal Enhancement, and Multiple Prints;67
6.6.3.11;2.6.3.11 Cross Sections;69
6.6.3.12;2.6.3.12 Underfill Filler Density;70
6.6.3.13;2.6.3.13 Shearing Test;70
6.7;2.7 Preassembly Underfill;71
6.8;2.8 Cu–Cu Direct Hybrid Bonding;75
6.9;2.9 Flip Chip Technology Versus FOWLP;76
6.10;2.10 Summary and Recommendations;77
6.11;References;79
7;3 Fan-in Wafer-Level Packaging Versus FOWLP;88
7.1;3.1 Introduction;88
7.2;3.2 Fan-in Wafer-Level Packaging (WLP);89
7.3;3.3 Wafer-Level Chip Scale Packages (WLCSPs);89
7.4;3.4 WLCSP Test Vehicle;90
7.4.1;3.4.1 The Chip;90
7.4.2;3.4.2 The WLCSP;90
7.4.3;3.4.3 WLCSP Key Process Steps;91
7.5;3.5 PCB Assembly of the WLCSP;92
7.6;3.6 Thermal Cycling Test of WLCSP-PCB Assembly;95
7.6.1;3.6.1 Thermal Cycling Condition;95
7.6.2;3.6.2 Crack Length Distribution of All Solder Joints;95
7.6.3;3.6.3 Crack Propagation of the Corner Solder Joint;96
7.6.4;3.6.4 Fatigue Crack Growth Rate;97
7.7;3.7 Fracture Characteristics of the Corner Solder Joint—Solder Material and Properties;100
7.8;3.8 Fracture Characteristics of the Corner Solder Joint—Geometry;102
7.9;3.9 Fracture Characteristics of the Corner Solder Joint—Elastic Thermal Fatigue Life Prediction Model (?K);103
7.9.1;3.9.1 Boundary Value Problem;103
7.9.2;3.9.2 Thermal Fatigue Life Prediction Model;105
7.9.3;3.9.3 Summary and Recommendations;107
7.10;3.10 Fracture Characteristics of the Corner Solder Joint—Plastic Thermal Fatigue Life Prediction Model (?J);108
7.10.1;3.10.1 Boundary Condition and Results;109
7.10.2;3.10.2 Thermal Fatigue Life Prediction Model;109
7.10.3;3.10.3 Summary and Recommendations;113
7.11;3.11 Fracture Characteristics of the Corner Solder Joint—Creep Thermal Fatigue Life Prediction Model (?W);114
7.11.1;3.11.1 Assumptions;114
7.11.2;3.11.2 Boundary Conditions;114
7.11.3;3.11.3 Deformed Shape, Stress, and Strain;115
7.11.4;3.11.4 Strain Energy Density Around the Crack Tip;116
7.11.5;3.11.5 A New and Simple Thermal Fatigue Life Prediction Model;121
7.11.6;3.11.6 Summary and Recommendation;123
7.12;3.12 Hitachi’s WLCSP;124
7.12.1;3.12.1 Hitachi’s WLCSP with Stress Relaxation Layer;124
7.12.2;3.12.2 Key Process Steps for Hitachi’s WLCSP;125
7.12.3;3.12.3 Reliability of Hitachi’s WLCSP;126
7.13;3.13 TSMC’s UFI WLCSP;127
7.13.1;3.13.1 TSMC’s WLCSP with Protection Layer;127
7.13.2;3.13.2 Key Process Steps for TSMC’s WLCSP;127
7.13.3;3.13.3 Reliability of TSMC’s WLCSP;127
7.14;3.14 Summary and Recommendations;128
7.15;References;130
8;4 Embedded Chip Packaging;133
8.1;4.1 Introduction;133
8.2;4.2 Chips Embedded in Laminated/Polyimide Panel Format;133
8.2.1;4.2.1 Advantages and Disadvantages;133
8.2.2;4.2.2 Various Chip Embedding Processes;134
8.2.3;4.2.3 Embedded Chip in Rigid Laminated Substrates;134
8.2.4;4.2.4 3D Embedded Chip in Flexible Polyimide Substrates;136
8.2.5;4.2.5 3D Embedded Stacking Chips in Flexible Polyimide Substrates;136
8.3;4.3 Chips Embedded in Si Wafer;137
8.3.1;4.3.1 Key Process Steps;137
8.3.2;4.3.2 Reliability of Chips Embedded in Si Wafer;137
8.4;4.4 Chips Embedded in Glass Panel;138
8.4.1;4.4.1 Key Process Steps;140
8.4.2;4.4.2 Reliability of Chips Embedded in Glass Panel;141
8.5;4.5 Summary and Recommendations;141
8.6;References;142
9;5 FOWLP: Chip-First and Die Face-Down;144
9.1;5.1 Introduction;144
9.2;5.2 Chip-First and Face-Down;146
9.3;5.3 Test Chips;147
9.4;5.4 Test Package;148
9.5;5.5 The Temporary Carrier;149
9.6;5.6 The 2-Side Thermal Release Tape and Pick and Place;151
9.7;5.7 EMC and Dispensing;152
9.8;5.8 Compression Molding and PMC;153
9.9;5.9 RDL;154
9.9.1;5.9.1 Debonding the Metal Carrier;154
9.9.2;5.9.2 Temporary Bonding of Another Glass Carrier;155
9.10;5.10 Solder Ball Mounting;157
9.11;5.11 Final Debonding;157
9.12;5.12 Summary and Recommendations;158
9.13;References;159
10;6 FOWLP: Chip-First and Die Face-Up;161
10.1;6.1 Introduction;161
10.2;6.2 Fan-Out of Chip Circuitries in Semiconductor Packaging;161
10.2.1;6.2.1 Advantages of FOWLP over PBGA;162
10.2.2;6.2.2 Advantages of FOWLP over WLCSP;162
10.3;6.3 FOWLP with Chip-First and Die Face-Up;162
10.4;6.4 Test Chip;163
10.5;6.5 Test Package;164
10.6;6.6 Chip-First (Die Face-Up) FOWLP Assembly Process;166
10.7;6.7 Assembly on the Test Chip Wafer;166
10.8;6.8 Assembly on the Reconstituted Wafer;167
10.8.1;6.8.1 Glass Carrier Wafer and LTHC Layer;167
10.8.2;6.8.2 Pick and Place;170
10.8.3;6.8.3 EMC Dispensing;171
10.8.4;6.8.4 Compression Molding, PMC, and Die Shift;173
10.8.5;6.8.5 Warpages;175
10.8.6;6.8.6 Cu Revealing;180
10.8.7;6.8.7 RDLs;181
10.8.8;6.8.8 Solder Ball Mounting;183
10.8.9;6.8.9 Debonding;184
10.9;6.9 PCB Assembly of FOWLP;185
10.9.1;6.9.1 PCB;185
10.9.2;6.9.2 Stencil and Printing;186
10.9.3;6.9.3 Pick and Place and Reflow;188
10.10;6.10 Thermal Performance of FOWLP;189
10.10.1;6.10.1 Structure;189
10.10.2;6.10.2 Material Properties;189
10.10.3;6.10.3 Boundary Conditions;190
10.10.4;6.10.4 Finite-Element Modeling and Analysis;190
10.10.5;6.10.5 Analysis Results;191
10.11;6.11 Reliability Assessments—Thermal Cycling Test;194
10.11.1;6.11.1 Test Setup;194
10.11.2;6.11.2 Test Results;196
10.12;6.12 Reliability Assessments—Drop Test;196
10.12.1;6.12.1 Test Setup;196
10.12.2;6.12.2 Test Results;198
10.13;6.13 Simulation on Thermal Cycling;199
10.14;6.14 Simulation on Shock (Drop);203
10.15;6.15 Summary and Recommendations;208
10.16;References;208
11;7 FOWLP: Chip-Last or RDL-First;211
11.1;7.1 Introduction;211
11.2;7.2 Reasons for Chip-Last or RDL-First FOWLP;212
11.3;7.3 Methods for Chip-Last or RDL-First FOWLP;212
11.4;7.4 Chip-Last (RDL-First) by PECVD and Cu Damascene + CMP;212
11.4.1;7.4.1 Key Process Flow;212
11.4.2;7.4.2 RDLs by PECVD and Cu Damascene + CMP;214
11.4.3;7.4.3 UBM/Cu Contact Pad/Solder Ball;215
11.5;7.5 Chip-Last (RDL-First) by Polymer and Cu Plating + Etching;216
11.5.1;7.5.1 Key Process Steps;216
11.5.2;7.5.2 RDLs by Polymer and Cu Plating + Etching;217
11.6;7.6 Chip-Last (RDL-First) by Hybrid RDLs;217
11.6.1;7.6.1 Key Process Steps;217
11.6.2;7.6.2 Examples of Hybrid RDLs;218
11.7;7.7 Summary and Recommendations;219
11.8;References;221
12;8 FOWLP: PoP;223
12.1;8.1 Introduction;223
12.2;8.2 STATS ChipPAC’s PoP for AP Chipset with eWLB;223
12.2.1;8.2.1 The Structure;224
12.2.2;8.2.2 Structural Warpages;224
12.2.3;8.2.3 Component-Level Reliability Assessments;226
12.2.4;8.2.4 Board-Level Reliability Assessments;226
12.3;8.3 TSMC’ PoP for AP Chipset with FOWLP;227
12.3.1;8.3.1 TSMC’ InFO;227
12.3.2;8.3.2 TSMC’ InFO-PoP for AP Chipset;227
12.4;8.4 Summary and Recommendations;231
12.5;References;232
13;9 Fan-Out Panel-Level Packaging (FOPLP);233
13.1;9.1 Introduction;233
13.2;9.2 J-Devices’ WFOP™;233
13.2.1;9.2.1 Structure of J-Devices’ WFOP™;234
13.2.2;9.2.2 Key Process Steps of J-Devices’ WFOP™;234
13.3;9.3 Fraunhofer’s FOPLP;235
13.3.1;9.3.1 Fraunhofer’s FOPLP Integration Line;235
13.3.2;9.3.2 Fraunhofer’s RDLs Key Process Steps;236
13.4;9.4 SPIL’s P-FO;238
13.4.1;9.4.1 Structure of SPIL’s P-FO;239
13.4.2;9.4.2 Key Process Steps of SPIL’s P-FO;239
13.5;9.5 Panel Versus Wafer;240
13.5.1;9.5.1 Issues of FOPLP;240
13.5.2;9.5.2 Reconstituted Wafers for High-End Applications;243
13.5.3;9.5.3 Reconstituted Wafers for Middle-End Applications;243
13.5.4;9.5.4 Reconstituted Panels for Low-End Applications;243
13.6;9.6 Summary and Recommendations;243
13.7;?References;245
14;10 3D Integration;247
14.1;10.1 Introduction;247
14.2;10.2 Overview and Outlooks of 3D IC Packaging;249
14.2.1;10.2.1 Chip Stacking by Wire Bonding;250
14.2.2;10.2.2 PoP;250
14.2.3;10.2.3 Chip-to-Chip Interconnects;253
14.2.4;10.2.4 Outlook of 3D IC Packaging;254
14.3;10.3 Overview, Challenges, and Outlook of 3D Si Integration;254
14.3.1;10.3.1 Issues of 3D Si Integration;254
14.3.2;10.3.2 Cu-to-Cu Bonding and Oxide-to-Oxide Bonding;255
14.3.3;10.3.3 R&D in 3D Si Integration;256
14.3.4;10.3.4 Outlooks of 3D Si Integration;257
14.3.5;10.3.5 Hybrid Bonding;257
14.4;10.4 Overview, Challenges, and Outlook of 3D IC Integration;258
14.4.1;10.4.1 Memory Stacking with TSVs;259
14.4.2;10.4.2 Wide I/O DRAM and Wide I/O 2;259
14.4.3;10.4.3 High-Bandwidth Memory (HBM);260
14.4.4;10.4.4 AMD’s Graphic Processor Unit with HBM;261
14.4.5;10.4.5 Nvidia’s Graphic Processor Unit with HBM2;262
14.4.6;10.4.6 Intel’s CPU with Micron’s HMC;263
14.4.7;10.4.7 Passive Interposer (2.5D IC Integration);264
14.4.8;10.4.8 Fabrication of TSVs;265
14.4.9;10.4.9 Fabrication of RDLs;266
14.4.10;10.4.10 Backside Processing and Assembly;267
14.4.11;10.4.11 Cu Revealing;268
14.4.12;10.4.12 Outlook of 2.5D/3D IC Integration;270
14.5;10.5 Supply Chains Before the TSV Era;271
14.5.1;10.5.1 Front-End-of-Line (FEOL);271
14.5.2;10.5.2 BEOL;271
14.5.3;10.5.3 OSATs;271
14.6;10.6 Supply Chains for the TSV Era—Who Makes the TSV?;272
14.6.1;10.6.1 TSVs Fabricated by the via-First Process;272
14.6.2;10.6.2 TSVs Fabricated by the via-Middle Process;272
14.6.3;10.6.3 TSVs Fabricated by the via-Last (from the Front-Side) Process;272
14.6.4;10.6.4 TSVs Fabricated by the via-Last (from the Backside) Process;272
14.6.5;10.6.5 How About the Passive TSV Interposers?;273
14.6.6;10.6.6 Who Wants to Fabricate the TSV for Passive Interposers?;273
14.7;10.7 Supply Chains for the TSV Era—Who Does the MEOL?;273
14.8;10.8 Outlook of HVM Supply Chains for TSVs and MEOL;274
14.9;10.9 Summary and Recommendations;274
14.10;References;275
15;11 3D IC Heterogeneous Integration by FOWLP;285
15.1;11.1 Introduction;285
15.2;11.2 Multichip Module (MCM);285
15.2.1;11.2.1 MCM-C;285
15.2.2;11.2.2 MCM-D;286
15.2.3;11.2.3 MCM-L;286
15.3;11.3 System-in-Package (SiP);286
15.3.1;11.3.1 Intention of SiP;286
15.3.2;11.3.2 Actual Applications of SiP;286
15.3.3;11.3.3 Potential Applications of SiP;287
15.4;11.4 System-on-Chip (SoC);287
15.4.1;11.4.1 Apple Application Processor (A10);287
15.4.2;11.4.2 Apple Application Processor (A11);287
15.5;11.5 Heterogeneous Integration;288
15.5.1;11.5.1 Heterogeneous Integration Versus SoC;288
15.5.2;11.5.2 Advantages of Heterogeneous Integration;290
15.6;11.6 Heterogeneous Integration on Organic Substrates;290
15.6.1;11.6.1 Amkor’s SiP for Automobiles;290
15.6.2;11.6.2 Apple Watch II (SiP) Assembled by ASE;290
15.6.3;11.6.3 Cisco’s ASIC and HBM on Organic Substrate;291
15.6.4;11.6.4 Intel’s CPU and Micron’s HMC on Organic Substrate;292
15.7;11.7 Heterogeneous Integration on Silicon Substrates (SoW);293
15.7.1;11.7.1 Leti’s SoW;293
15.7.2;11.7.2 Xilinx/TSMC’s CoWoS;294
15.7.3;11.7.3 Analog Devices’ MEMS on ASIC Wafer;294
15.7.4;11.7.4 AMD’s GPU and Hynix’s HBM on TSV-Interposer;296
15.7.5;11.7.5 Nvidia’s GPU and Samsung’s HBM2 on TSV-Interposer;297
15.7.6;11.7.6 UCLA’s SoW;298
15.8;11.8 Heterogeneous Integration on RDLs;298
15.8.1;11.8.1 Xilinx/SPIL’s TSV-Less SLIT;298
15.8.2;11.8.2 Amkor’s TSV-Less SLIM;301
15.8.3;11.8.3 Intel’s TSV-Less EMIB (RDL) for FPGA and HBM;302
15.8.4;11.8.4 EMIB (RDL) for Intel’s CPU and AMD’s GPU;303
15.8.5;11.8.5 STATS ChipPAC’s FOFC-eWLB;304
15.8.6;11.8.6 ASE’s FOCoS;305
15.8.7;11.8.7 MediaTek’s RDLs by FOWLP;306
15.9;11.9 3D IC Heterogeneous Integration by FOWLP;306
15.9.1;11.9.1 Application Processor with FOWLP;307
15.9.2;11.9.2 Application Processor by 3D IC Heterogeneous Integration with FOWLP;309
15.10;11.10 3D IC High-Performance Heterogeneous Integration by FOWLP;314
15.10.1;11.10.1 High-Performance 3D IC Heterogeneous Integration System;314
15.10.2;11.10.2 Manufacturing Process;314
15.10.3;11.10.3 Advantages of the New Manufacturing Process;316
15.11;11.11 Summary and Recommendations;316
15.12;References;317