Li / Goyal 3D Microelectronic Packaging

From Fundamentals to Applications
1. Auflage 2017
ISBN: 978-3-319-44586-1
Verlag: Springer Nature Switzerland
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 57, 465 Seiten

Reihe: Springer Series in Advanced Microelectronics

This volume provides a comprehensive reference for graduate students and professionals in both academia and industry on the fundamentals, processing details, and applications of 3D microelectronic packaging, an industry trend for future microelectronic packages. Chapters written by experts cover the most recent research results and industry progress in the following areas: TSV, die processing, micro bumps, direct bonding, thermal compression bonding, advanced materials, heat dissipation, thermal management, thermal mechanical modeling, quality, reliability, fault isolation, and failure analysis of 3D microelectronic packages. Numerous images, tables, and didactic schematics are included throughout. This essential volume equips readers with an in-depth understanding of all aspects of 3D packaging, including packaging architecture, processing, thermal mechanical and moisture related reliability concerns, common failures, developing areas, and future challenges, providing insights into key areas for future research and development. 

Autoren/Hrsg.

Li, Yan

Goyal, Deepak

Inhaltsverzeichnis

1;Contents;6
2;Contributors;8
3;About the Authors;10
4;Chapter 1: Introduction to 3D Microelectronic Packaging;11
4.1;1.1 Introduction;11
4.2;1.2 Why 3D Packaging;13
4.2.1;1.2.1 Moore´s Law;13
4.2.2;1.2.2 Small Form Factor Requires 3D Packaging;14
4.2.3;1.2.3 Improved System Performance with Reduced Power;15
4.3;1.3 3D Microelectronic Packaging Architectures;16
4.3.1;1.3.1 Die-to-Die 3D Integration;16
4.3.2;1.3.2 Package-to-Package 3D Integration;19
4.3.3;1.3.3 Heterogeneous 3D Integration;19
4.4;1.4 3D Microelectronic Packaging Challenges;21
4.4.1;1.4.1 Assembly Process, Yield, Test, and Cost Challenges;21
4.4.2;1.4.2 Thermal Management, Package Design, and Modeling Challenges;21
4.4.3;1.4.3 Material and Substrate Challenges;22
4.4.4;1.4.4 Quality, Reliability, and Failure Analysis Challenges;22
4.4.5;1.4.5 Summary;23
4.5;References;24
5;Chapter 2: 3D Packaging Architectures and Assembly Process Design;26
5.1;2.1 Introduction;27
5.2;2.2 3D TSV-Based Architectures: Advantages and Limitations;34
5.3;2.3 Methods of Fabrication and Other TSV Attributes;39
5.4;2.4 Assembly Process Flows;44
5.5;2.5 Manufacturing Yields and the Role of Test;48
5.6;2.6 Challenges with 3D TSV Architectures;51
5.7;2.7 Summary;52
5.8;References;52
6;Chapter 3: Materials and Processing of TSV;56
6.1;3.1 Introduction;56
6.2;3.2 Overview of TSV Materials and Processes;57
6.3;3.3 Fabrication of TSV and TSV Assembly;58
6.3.1;3.3.1 Creating a Via or Trench in Si Wafer;59
6.3.1.1;3.3.1.1 Laser Drilling;60
6.3.1.2;3.3.1.2 Powder Blast Micromachining;61
6.3.1.3;3.3.1.3 Wet Etching;62
6.3.1.4;3.3.1.4 Plasma-Based Methods;63
6.3.2;3.3.2 Sequential Filling of Si Via;66
6.3.3;3.3.3 Planarization and Die-Thinning;70
6.4;3.4 Flow Process for Fabricating TSVs and Integration of Dies;71
6.4.1;3.4.1 Sequence of Flow Process;71
6.4.2;3.4.2 Integration of Dies Comprising TSVs;73
6.5;3.5 Summary;74
6.6;References;75
7;Chapter 4: Microstructural and Reliability Issues of TSV;79
7.1;4.1 Introduction;79
7.2;4.2 Microstructural Characterization and Stress Measurement;80
7.2.1;4.2.1 Microstructural Characterization;80
7.2.2;4.2.2 Measurement of Stress State;82
7.2.2.1;4.2.2.1 Wafer Curvature Method;82
7.2.2.2;4.2.2.2 Micro-Raman Spectroscopy;83
7.2.2.3;4.2.2.3 X-Ray Diffraction-Based Techniques;84
7.2.2.4;4.2.2.4 Stress Metrology Challenges;85
7.3;4.3 Reliability Issues Associated with TSVs;85
7.3.1;4.3.1 Stresses in TSVs;85
7.3.1.1;4.3.1.1 Origin and Effect of Stresses;85
7.3.1.2;4.3.1.2 Microstructure and Stresses;89
7.3.1.3;4.3.1.3 Metal Pumping: Extrusion or Intrusion of TSVs;91
7.3.2;4.3.2 Electromigration Related Effects;96
7.4;4.4 Towards Atomistically informed Reliability Modeling of TSVs;99
7.4.1;4.4.1 The CPFE Method;99
7.4.2;4.4.2 The PFC Method;100
7.5;4.5 Summary;102
7.6;References;103
8;Chapter 5: Fundamentals and Failures in Die Preparation for 3D Packaging;108
8.1;5.1 Introduction;108
8.2;5.2 Brief Overview of TSV Wafer Fabrication Processes;109
8.3;5.3 Wafer Buckling and Wrinkling;115
8.4;5.4 Thermal Sliding Wafer Debonding;117
8.5;5.5 Wafer Laser Scribe;121
8.6;5.6 Wafer Saw Process;124
8.7;5.7 Wafer Die Ejector;129
8.8;5.8 Conclusions;131
8.9;References;132
9;Chapter 6: Direct Cu to Cu Bonding and Other Alternative Bonding Techniques in 3D Packaging;136
9.1;6.1 Introduction;136
9.2;6.2 Solder-Based vs. Solder-Less Bonding: Pros and Cons;137
9.3;6.3 Stacking and Bonding Schemes, Technologies, and Applications;139
9.4;6.4 Thermo-Compression Bonding (Diffusion Bonding): Material Fundamentals and Microstructure Effects;140
9.5;6.5 Passivation with Capping Layers (SAMs and Metals);143
9.6;6.6 Surface Activated Bonding (SAB) Processes;144
9.6.1;6.6.1 Cu/Dielectric Hybrid Bonding;148
9.6.2;6.6.2 Cu/SiO2 Hybrid Bonding;149
9.6.3;6.6.3 Cu/Adhesive Hybrid Bonding;153
9.7;6.7 Alternative Bonding Techniques: Insertion Bonding;155
9.8;6.8 Cu-Cu Bonding: Equipment Landscape and State of the Art;157
9.9;6.9 Chapter Summary and Future Recommendations;157
9.10;References;158
10;Chapter 7: Fundamentals of Thermal Compression Bonding Technology and Process Materials for 2.5/3D Packages;163
10.1;7.1 Introduction;163
10.2;7.2 Background;164
10.2.1;7.2.1 Overview of 3D Package Configuration;165
10.2.2;7.2.2 Fundamentals of Thermal Compression Bonding Technology;168
10.2.2.1;7.2.2.1 Technical Challenges of Mass Reflow Process Compared with TCB;168
10.2.2.2;7.2.2.2 Thermal Compression Bonding Tool;172
10.2.2.3;7.2.2.3 Thermal Compression Bonding Process;174
10.2.3;7.2.3 Fundamentals of Process Materials;179
10.2.3.1;7.2.3.1 Introduction;179
10.2.3.2;7.2.3.2 Basic Properties Measurement;179
10.2.3.3;7.2.3.3 Wetting Study;183
10.2.3.4;7.2.3.4 Void Formation Study;185
10.3;7.3 Principles of Materials Formulation;186
10.3.1;7.3.1 Water-Soluble Flux;187
10.3.2;7.3.2 No-Clean Flux;188
10.3.3;7.3.3 Capillary Underfill;189
10.3.4;7.3.4 Epoxy Flux (No-Flow Underfill or Non-Conductive Paste);190
10.3.5;7.3.5 Pre-Applied Epoxy-Based Materials (Non-Conductive Film and B-Stage Material);192
10.4;7.4 Assembly Process Design;195
10.4.1;7.4.1 Introduction;195
10.4.2;7.4.2 TCB Assembly Building Block;196
10.4.3;7.4.3 TCB Assembly Building Block Design and Development;198
10.4.3.1;7.4.3.1 TSV Memory Stacking;199
10.4.3.2;7.4.3.2 Memory Module to Logic or Silicon Interposer Attachment;203
10.5;7.5 Summary and Discussion;206
10.6;References;207
11;Chapter 8: Fundamentals of Solder Alloys in 3D Packaging;210
11.1;8.1 The Microbumping Process;210
11.2;8.2 The Solder Alloys in Microbump;215
11.3;8.3 The Formation of Intermetallic Compounds in the As-Produced Microbump;215
11.4;8.4 Microstructure Variation of Microbump Under Thermal Mechanical Conditions;220
11.5;8.5 The Microstructure and Failure Mechanism of Microbump;222
11.6;8.6 Summary and Future Challenge;224
11.7;References;225
12;Chapter 9: Fundamentals of Electromigration in Interconnects of 3D Packaging;228
12.1;9.1 Introduction;228
12.2;9.2 Key Modulators for EM in Solder Joints;229
12.2.1;9.2.1 Typical EM Fail Caused by Sn Diffusion;229
12.2.2;9.2.2 EM Fail Caused by Metallization Dissolution;232
12.3;9.3 EM in Solder Joints of 3D Packaging;237
12.3.1;9.3.1 EM Damage due to Sn Flux Divergence in Micro Bumps;237
12.3.2;9.3.2 The Transformation of Full IMC Joint Under EM;238
12.3.3;9.3.3 Thermomigration Accompanied by EM;241
12.4;9.4 EM in TSV of 3D Packaging;243
12.4.1;9.4.1 EM for Cu Damascene Interconnects;244
12.4.2;9.4.2 EM Failure in TSV;245
12.5;9.5 Summary;247
12.6;References;248
13;Chapter 10: Fundamentals of Heat Dissipation in 3D IC Packaging;250
13.1;10.1 Introduction;250
13.2;10.2 Thermal Performance Parameters for 3D ICs;251
13.3;10.3 Air Cooling of 3D ICs;253
13.4;10.4 Jet Impingement and Spray Cooling;254
13.5;10.5 Microchannel Cooling;254
13.6;10.6 Thermal Design Considerations in 3D IC Architectures;255
13.6.1;10.6.1 Thermal Considerations in TSV Placements;257
13.6.2;10.6.2 Thermal Analysis Tools for 3D ICs;257
13.6.3;10.6.3 Performance Considerations;257
13.7;10.7 Liquid Cooling with Integrated Microchannels;258
13.7.1;10.7.1 Variable Fin Density in Microchannel Passages;258
13.7.2;10.7.2 Two-Phase Cooling;262
13.8;10.8 Future Directions;262
13.9;References;263
14;Chapter 11: Fundamentals of Advanced Materials and Processes in Organic Substrate Technology;266
14.1;11.1 Introduction;266
14.2;11.2 Overview of Substrate Technology Evolution;267
14.3;11.3 Organic Substrate Materials;267
14.3.1;11.3.1 Materials Employed in Organic Substrate Production;267
14.3.2;11.3.2 General Considerations;269
14.3.3;11.3.3 Substrate and PWB Cores;274
14.3.3.1;11.3.3.1 Reinforcement Materials;275
14.3.3.2;11.3.3.2 Resin Systems;278
14.3.3.3;11.3.3.3 Conductors;281
14.3.4;11.3.4 Dielectric Materials;282
14.3.5;11.3.5 PTH and Via Filling Materials;284
14.3.6;11.3.6 Solder Mask Materials;285
14.3.7;11.3.7 Surface Finishes;286
14.3.8;11.3.8 Summary;286
14.4;11.4 Organic Substrate Fabrication;289
14.4.1;11.4.1 Substrate Raw Material Selection and Preparation;290
14.4.2;11.4.2 Inner Layer Imaging;292
14.4.3;11.4.3 Multilayer Buildup;292
14.4.4;11.4.4 Soldermask and Surface Finish Application;294
14.4.5;11.4.5 Final Sizing, Testing, Inspection, and Shipment;295
14.5;References;295
15;Chapter 12: Die and Package Level Thermal and Thermal/Moisture Stresses in 3D Packaging: Modeling and Characterization;297
15.1;12.1 Introduction;299
15.2;12.2 Thermal Stress and Its Effects on TSV Structures;300
15.2.1;12.2.1 Introduction;300
15.2.2;12.2.2 Characteristics of TSV Stress by Semi-analytic and Numerical Solutions;300
15.2.3;12.2.3 Measurement of Thermal Stress;302
15.2.4;12.2.4 Effect of Thermal Stress on Carrier Mobility and Keep-Out Zone;305
15.2.5;12.2.5 Thermal Stress Induced via Extrusion;306
15.3;12.3 Thermal Stresses and Warpage Control at Package Level;309
15.3.1;12.3.1 Introduction;309
15.3.2;12.3.2 Thermal Stresses in a Multilayered Structure;310
15.3.3;12.3.3 Warpage Mechanism and Control Methods;312
15.3.4;12.3.4 A Capped-Die Approach for Warpage Control;314
15.3.5;12.3.5 Warpage Characterization by Experimental Testing;315
15.3.6;12.3.6 Numerical Modeling for Optimizing Warpage Control Design;317
15.3.6.1;12.3.6.1 Comparison of Different Control Methods;317
15.3.6.2;12.3.6.2 Optimization of Cap Thickness to Achieve Warpage-Free Packages;318
15.3.6.3;12.3.6.3 Overcontrolled Warpage;319
15.3.6.4;12.3.6.4 Warpage-Free Control for Coreless Substrate;319
15.4;12.4 Integrated Stress Analysis for Combining Moisture and Thermal Effects;321
15.4.1;12.4.1 Introduction;321
15.4.2;12.4.2 Moisture Diffusion;322
15.4.3;12.4.3 Moisture-Induced Strain and Effective Stress Theory;324
15.4.4;12.4.4 Vapor Pressure Modeling;325
15.4.5;12.4.5 Governing Equation for Integrated Stress Analysis;327
15.4.6;12.4.6 Case Studies;327
15.5;12.5 Summary;331
15.6;References;333
16;Chapter 13: Processing and Reliability of Solder Interconnections in Stacked Packaging;337
16.1;13.1 Introduction;337
16.1.1;13.1.1 Miniaturization and Functionality Trends;337
16.1.2;13.1.2 3D Packaging Variations;339
16.1.3;13.1.3 Applications Drive PoP and PoPoP Component Requirements;340
16.2;13.2 Soldering Assembly Processes;341
16.2.1;13.2.1 Solder Alloys;342
16.2.1.1;13.2.1.1 Sn-Pb Solders;342
16.2.1.2;13.2.1.2 Pb-Free Solders: ``High Ag´´ Alloys;342
16.2.1.3;13.2.1.3 Pb-Free Solders: ``Low Ag´´ Alloys;343
16.2.1.4;13.2.1.4 Mixed Solder Joints;343
16.2.2;13.2.2 Fluxes and Pastes;344
16.2.3;13.2.3 Assembly Methodologies;346
16.2.3.1;13.2.3.1 Stacked Packages;346
16.2.3.2;13.2.3.2 Soldering Assembly (Second-Level Interconnections);348
16.2.3.3;13.2.3.3 Cleaning Considerations;348
16.2.3.4;13.2.3.4 Rework;349
16.2.4;13.2.4 Inspection Techniques;350
16.2.5;13.2.5 Underfill, Conformal Coatings, and Encapsulants;352
16.2.5.1;13.2.5.1 Underfill;352
16.2.5.2;13.2.5.2 Conformal Coatings;354
16.2.5.3;13.2.5.3 Encapsulants;355
16.2.6;13.2.6 Warpage Effects;355
16.3;13.3 Solder Joint Reliability;358
16.3.1;13.3.1 Environments;358
16.3.1.1;13.3.1.1 Use Conditions;358
16.3.1.2;13.3.1.2 Consumer Electronics;359
16.3.1.3;13.3.1.3 High-Reliability Electronics;360
16.3.1.4;13.3.1.4 Accelerated Aging;361
16.3.2;13.3.2 Underfill, Conformal Coatings, and Encapsulants;362
16.3.2.1;13.3.2.1 Materials Properties;362
16.3.2.2;13.3.2.2 Geometry;363
16.3.3;13.3.3 Reliability Studies;363
16.3.3.1;13.3.3.1 Mechanical Shock and Vibration;363
16.3.3.1.1;Solder Alloy Effects;364
16.3.3.1.2;Surface Finish Effects;364
16.3.3.1.3;Importance of Test Standards;365
16.3.3.2;13.3.3.2 Temperature Cycling;365
16.3.3.2.1;Temperature Limits;366
16.3.3.2.2;Test Vehicle Construction;366
16.3.3.2.3;Materials Set for Computational Modeling;367
16.3.3.2.4;Solder Alloy Fatigue Properties;367
16.3.3.2.5;Effects of Alloy Composition and Underfill on Solder Joint Reliability: An Empirical Study;368
16.4;13.4 Summary and Future Trends;373
16.4.1;13.4.1 Summary;373
16.4.2;13.4.2 Future Trends;374
16.5;References;375
17;Chapter 14: Interconnect Quality and Reliability of 3D Packaging;378
17.1;14.1 Introduction;378
17.2;14.2 Quality Challenges for 3D Packaging;379
17.3;14.3 Quality and Reliability of Microbumps;383
17.3.1;14.3.1 Type 1: Cu/Sn/Cu;383
17.3.1.1;14.3.1.1 Microstructure of Cu-Sn IMCs-Based Microbump;383
17.3.1.2;14.3.1.2 Microstructural Characteristics of Cu6Sn5 in Microbump;383
17.3.1.3;14.3.1.3 Kirkendall Void and Porous Void Formation in Cu3Sn;386
17.3.1.4;14.3.1.4 Anisotropic Effect in Microbump;387
17.3.2;14.3.2 Type 2: Ni/Sn/Ni;391
17.3.3;14.3.3 Type 3: Cu/Sn/Ni;394
17.3.4;14.3.4 Type 4: Cu/Ni/Sn/Ni/Cu;396
17.3.4.1;14.3.4.1 Typical Composition Parameters of Cu/Ni/Sn/Ni/Cu Microbumps;396
17.3.4.2;14.3.4.2 IMC/Solder Interfacial Crack Formation;397
17.3.4.3;14.3.4.3 Ni as Effective Diffusion Barrier to Suppress Kirkendall Void Formation;398
17.3.5;14.3.5 Concluding Remarks;400
17.4;14.4 Field Performance Prediction of 3D Packaging;400
17.5;14.5 Electromigration Reliability for 3D IC Packaging;402
17.5.1;14.5.1 Introduction on Electromigration;403
17.5.1.1;14.5.1.1 Back Stress;403
17.5.1.2;14.5.1.2 Statistical Analysis by Weibull Distribution Function in Reliability Study;404
17.5.2;14.5.2 Experimental Studies of Electromigration in Al and Cu Interconnects;405
17.5.3;14.5.3 Electromigration in Flip Chip Solder Joints;406
17.5.4;14.5.4 System Level Electromigration Studies in 3D IC Packaging;406
17.5.4.1;14.5.4.1 Electromigration in Microbumps;407
17.5.4.2;14.5.4.2 Electromigration in TSVs;408
17.5.5;14.5.5 System Level Weak-Link Failure in 2.5D Integrated Circuits;409
17.5.6;14.5.6 Concluding Remarks;412
17.6;14.6 Thermomigration in 3D IC Packaging;412
17.6.1;14.6.1 Introduction;412
17.6.2;14.6.2 Fundamentals of Thermomigration;413
17.6.2.1;14.6.2.1 Traditional TM Studies;413
17.6.3;14.6.3 Thermomigration Studies in 3D IC Packaging;415
17.6.3.1;14.6.3.1 Thermomigration in Microbumps;415
17.6.3.2;14.6.3.2 Thermomigration in TSV;417
17.6.3.3;14.6.3.3 Thermomigration Induced by Thermal Crosstalk;418
17.6.4;14.6.4 Concluding Remarks;418
17.7;References;419
18;Chapter 15: Fault Isolation and Failure Analysis of 3D Packaging;424
18.1;15.1 Introduction;424
18.2;15.2 Fault Isolation and Failure Analysis Challenges for Advanced 3D Packages;426
18.3;15.3 The Application of Nondestructive FI and FA Techniques to 3D Microelectronic Packages;427
18.3.1;15.3.1 Nondestructive Fault Isolation Techniques for Electrical Failures in 3D Microelectronic Packages;427
18.3.1.1;15.3.1.1 Time-Domain Reflectometry;427
18.3.1.2;15.3.1.2 Electro Optic Terahertz Pulse Reflectometry;429
18.3.1.3;15.3.1.3 Lock-in Thermography;431
18.3.1.4;15.3.1.4 Scanning Superconducting Quantum Interference Device Microscopy;432
18.3.2;15.3.2 High Resolution Non-destructive Imaging Techniques for 3D Microelectronic Packages;434
18.3.2.1;15.3.2.1 Scanning Acoustic Microscopy;435
18.3.2.2;15.3.2.2 2D X-Ray Radiography;442
18.3.2.3;15.3.2.3 3D X-Ray Computed Tomography (CT);444
18.4;15.4 The Application of Sample Preparation and Material Analysis Techniques to 3D Microelectronic Packages;447
18.4.1;15.4.1 Sample Preparation Techniques;447
18.4.1.1;15.4.1.1 Nanosecond (ns) and Femtosecond (fs) Laser Ablation Techniques;448
18.4.1.2;15.4.1.2 Plasma Focused Ion Beam (FIB);448
18.4.1.3;15.4.1.3 Broad-Beam Argon Ion Milling (EDX);449
18.4.2;15.4.2 Material Analysis Techniques;449
18.4.2.1;15.4.2.1 Energy-Dispersive X-ray Spectroscopy (EDX);450
18.4.2.2;15.4.2.2 X-ray Photoelectron Spectroscopy (XPS) and Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS);451
18.4.2.3;15.4.2.3 Electron Backscatter Diffraction (EBSD);452
18.5;15.5 Failure Analysis Strategies for 3D Packages;454
18.5.1;15.5.1 Understanding the Package Assembly Process, Reliability Stress, and Failure Rate Distribution;454
18.5.2;15.5.2 Efficient FI-FA Flow to Identify Defects;456
18.5.3;15.5.3 In-Depth Failure Mechanism and Root Cause Understanding to Provide Solution Paths;458
18.6;15.6 Conclusions;459
18.7;References;460
19;Index;463