Narendra / Chandrakasan Leakage in Nanometer CMOS Technologies

2006
ISBN: 978-0-387-28133-9
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 308 Seiten, eBook

Reihe: Integrated Circuits and Systems

Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles.

Also treated are the resulting effects so the reader understands the effectiveness of leakage power reduction solutions under these different conditions.

Case studies supply real-world examples that reap the benefits of leakage power reduction solutions as the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

Zielgruppe

Research

Autoren/Hrsg.

Narendra, Siva G.

Chandrakasan, Anantha P.

Inhaltsverzeichnis

Taxonomy of Leakage: Sources, Impact, and Solutions.- Leakage Dependence on Input Vector.- Power Gating and Dynamic Voltage Scaling.- Methodologies for Power Gating.- Body Biasing.- Process Variation and Adaptive Design.- Memory Leakage Reduction.- Active Leakage Reduction and Multi-Performance Devices.- Impact of Leakage Power and Variation on Testing.- Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors.- Case Study: Leakage Reduction in the Intel Xscale Microprocessor.- Transistor Design to Reduce Leakage.