Popovici / Rousseau / Jerraya Embedded Software Design and Programming of Multiprocessor System-on-Chip

Simulink and System C Case Studies
1. Auflage 2010
ISBN: 978-1-4419-5567-8
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 290 Seiten

Reihe: Embedded Systems

Current multimedia and telecom applications require complex, heterogeneous multiprocessor system on chip (MPSoC) architectures with specific communication infrastructure in order to achieve the required performance. Heterogeneous MPSoC includes different types of processing units (DSP, microcontroller, ASIP) and different communication schemes (fast links, non standard memory organization and access). Programming an MPSoC requires the generation of efficient software running on MPSoC from a high level environment, by using the characteristics of the architecture. This task is known to be tedious and error prone, because it requires a combination of high level programming environments with low level software design. This book gives an overview of concepts related to embedded software design for MPSoC. It details a full software design approach, allowing systematic, high-level mapping of software applications on heterogeneous MPSoC. This approach is based on gradual refinement of hardware/software interfaces and simulation models allowing to validate the software at different abstraction levels. This book combines Simulink for high level programming and SystemC for the low level software development. This approach is illustrated with multiple examples of application software and MPSoC architectures that can be used for deep understanding of software design for MPSoC.

Autoren/Hrsg.

Popovici, Katalin

Rousseau, Frédéric

Jerraya, Ahmed A.

Wolf, Marilyn

Inhaltsverzeichnis

1;Acknowledgments;6
2;Contents;8
3;List of Figures;12
4;List of Tables;16
5;1 Embedded Systems Design: Hardware and Software Interaction;17
5.1;1.1 Introduction;17
5.2;1.2 From Simple Compiler to Software Design for MPSoC;23
5.3;1.3 MPSoC Programming Steps;29
5.4;1.4 Hardware/Software Abstraction Levels;32
5.4.1;1.4.1 The Concept of Hardware/Software Interface;34
5.4.2;1.4.2 Software Execution Models with Abstract Hardware/Software Interfaces;36
5.5;1.5 The Concept of Mixed Architecture/Application Model;40
5.5.1;1.5.1 Definition of the Mixed Architecture/Application Model;40
5.5.2;1.5.2 Execution Model for Mixed Architecture/Application Model;41
5.5.2.1;1.5.2.1 Execution Model Described in Simulink;41
5.5.2.2;1.5.2.2 Execution Model Described in SystemC;44
5.6;1.6 Examples of Heterogeneous MPSoC Architectures;47
5.6.1;1.6.1 1AX with AMBA Bus;47
5.6.2;1.6.2 Diopsis RDT with AMBA Bus;49
5.6.3;1.6.3 Diopsis R2DT with NoC;52
5.7;1.7 Examples of Multimedia Applications;55
5.7.1;1.7.1 Token Ring Functional Specification;56
5.7.2;1.7.2 Motion JPEG Decoder Functional Specification;57
5.7.3;1.7.3 H.264 Encoder Functional Specification;59
5.8;1.8 Conclusions;63
6;2 Basics;65
6.1;2.1 The MPSoC Architecture;65
6.2;2.2 Programming Models for MPSoC;67
6.2.1;2.2.1 Programming Models Used in Software;70
6.2.2;2.2.2 Programming Models for SoC Design;71
6.2.3;2.2.3 Defining a Programming Model for SoC;72
6.2.4;2.2.4 Existing Programming Models;74
6.2.4.1;2.2.4.1 Message-Passing Interface (MPI);74
6.2.4.2;2.2.4.2 Multi-core Communications API (MCAPI);75
6.2.4.3;2.2.4.3 Y-Chart Application Programmer's Interface (YAPI);76
6.2.4.4;2.2.4.4 Task Transaction Level (TTL);76
6.2.4.5;2.2.4.5 Distributed System Object Component (DSOC);76
6.2.4.6;2.2.4.6 Compute Unified Device Architecture (CUDA);77
6.2.4.7;2.2.4.7 Open Computing Language (OpenCL);78
6.2.4.8;2.2.4.8 Open Multi-processing (OpenMP);79
6.2.4.9;2.2.4.9 Transaction-Level Modeling (TLM);80
6.2.4.10;2.2.4.10 Other Examples of Programming Models;80
6.3;2.3 Software Stack for MPSoC;81
6.3.1;2.3.1 Definition of the Software Stack;81
6.3.2;2.3.2 Software Stack Organization;82
6.3.2.1;2.3.2.1 Application Layer;82
6.3.2.2;2.3.2.2 HdS Layer;83
6.4;2.4 Hardware Components;85
6.4.1;2.4.1 Computing Unit;85
6.4.1.1;2.4.1.1 General-Purpose Processor;89
6.4.1.2;2.4.1.2 Application-Specific Instruction Set Processor;89
6.4.1.3;2.4.1.3 Digital Signal Processor;91
6.4.1.4;2.4.1.4 Microcontroller;92
6.4.2;2.4.2 Memory;93
6.4.3;2.4.3 Interconnect;96
6.5;2.5 Software Layers;100
6.5.1;2.5.1 Hardware Abstraction Layer;102
6.5.2;2.5.2 Operating System;103
6.5.3;2.5.3 Communication and Middleware;108
6.5.4;2.5.4 Legacy Software and Programming Models;108
6.6;2.6 Conclusions;108
7;3 System Architecture Design;109
7.1;3.1 Introduction;109
7.1.1;3.1.1 Mapping Application on Architecture;109
7.1.1.1;3.1.1.1 The Mapping;109
7.1.1.2;3.1.1.2 The Design Space Exploration;112
7.1.2;3.1.2 Definition of the System Architecture;113
7.1.3;3.1.3 Global Organization of the System Architecture;114
7.2;3.2 Basic Components of the System Architecture Model;117
7.2.1;3.2.1 Functions;117
7.2.2;3.2.2 Communication;118
7.3;3.3 Modeling System Architecture in Simulink;118
7.3.1;3.3.1 Writing Style, Design Rules, and Constraints in Simulink;118
7.3.1.1;3.3.1.1 Constraints on the Simulink Standard Blocks;118
7.3.1.2;3.3.1.2 Constraints on the S-Functions;119
7.3.1.3;3.3.1.3 Constraints on the Communication;120
7.3.2;3.3.2 Software at System Architecture Level;120
7.3.3;3.3.3 Hardware at System Architecture Level;121
7.3.4;3.3.4 Hardware--Software Interface at System Architecture Level;122
7.4;3.4 Execution Model of the System Architecture;122
7.5;3.5 Design Space Exploration of System Architecture;122
7.5.1;3.5.1 Goal of Performance Evaluation;122
7.5.2;3.5.2 Architecture/Application Parameters;123
7.5.3;3.5.3 Performance Measurements;125
7.5.4;3.5.4 Design Space Exploration;126
7.6;3.6 Application Examples at the System Architecture Level;127
7.6.1;3.6.1 Motion JPEG Application on Diopsis RDT;127
7.6.2;3.6.2 H.264 Application on Diopsis R2DT;130
7.7;3.7 State of the Art and Research Perspectives;134
7.7.1;3.7.1 State of the Art;134
7.7.2;3.7.2 Research Perspectives;135
7.8;3.8 Conclusions;136
8;4 Virtual Architecture Design;138
8.1;4.1 Introduction;138
8.1.1;4.1.1 Definition of the Virtual Architecture;138
8.1.2;4.1.2 Global Organization of the Virtual Architecture;139
8.2;4.2 Basic Components of the Virtual Architecture Model;140
8.2.1;4.2.1 Software Components;141
8.2.2;4.2.2 Hardware Components;141
8.3;4.3 Modeling Virtual Architecture in SystemC;142
8.3.1;4.3.1 Software at Virtual Architecture Level;142
8.3.2;4.3.2 Hardware at Virtual Architecture Level;145
8.3.3;4.3.3 Hardware--Software Interface at Virtual Architecture Level;149
8.4;4.4 Execution Model of the Virtual Architecture;149
8.5;4.5 Design Space Exploration of Virtual Architecture;151
8.5.1;4.5.1 Goal of Performance Evaluation;151
8.5.2;4.5.2 Architecture/Application Parameters;151
8.5.3;4.5.3 Performance Measurements;152
8.5.4;4.5.4 Design Space Exploration;154
8.6;4.6 Application Examples at the Virtual Architecture Level;154
8.6.1;4.6.1 Motion JPEG Application on Diopsis RDT;154
8.6.2;4.6.2 H.264 Application on Diopsis R2DT;158
8.7;4.7 State of the Art and Research Perspectives;162
8.7.1;4.7.1 State of the Art;162
8.7.2;4.7.2 Research Perspectives;163
8.8;4.8 Conclusions;164
9;5 Transaction-Accurate Architecture Design;166
9.1;5.1 Introduction;166
9.1.1;5.1.1 Definition of the Transaction-Accurate Architecture;167
9.1.2;5.1.2 Global Organization of the Transaction-Accurate Architecture;167
9.2;5.2 Basic Components of the Transaction-Accurate Architecture Model;169
9.2.1;5.2.1 Software Components;170
9.2.2;5.2.2 Hardware Components;170
9.3;5.3 Modeling Transaction-Accurate Architecture in SystemC;171
9.3.1;5.3.1 Software at Transaction-Accurate Architecture Level;171
9.3.2;5.3.2 Hardware at Transaction-Accurate Architecture Level;176
9.3.3;5.3.3 Hardware--Software Interface at Transaction-Accurate Architecture Level;179
9.4;5.4 Execution Model of the Transaction-Accurate Architecture;179
9.5;5.5 Design Space Exploration of Transaction-Accurate Architecture;181
9.5.1;5.5.1 Goal of Performance Evaluation;181
9.5.2;5.5.2 Architecture/Application Parameters;182
9.5.3;5.5.3 Performance Measurements;182
9.5.4;5.5.4 Design Space Exploration;183
9.6;5.6 Application Examples at the Transaction-Accurate Architecture Level;184
9.6.1;5.6.1 Motion JPEG Application on Diopsis RDT;184
9.6.2;5.6.2 H.264 Application on Diopsis R2DT;187
9.7;5.7 State of the Art and Research Perspectives;195
9.7.1;5.7.1 State of the Art;195
9.7.2;5.7.2 Research Perspectives;196
9.8;5.8 Conclusions;197
10;6 Virtual Prototype Design;198
10.1;6.1 Introduction;198
10.1.1;6.1.1 Definition of the Virtual Prototype;198
10.1.2;6.1.2 Global Organization of the Virtual Prototype;200
10.2;6.2 Basic Components of the Virtual Prototype Model;200
10.2.1;6.2.1 Software Components;200
10.2.2;6.2.2 Hardware Components;201
10.3;6.3 Modeling Virtual Prototype in SystemC;202
10.3.1;6.3.1 Software at Virtual Prototype Level;202
10.3.1.1;6.3.1.1 Loading Software Image in Memory;206
10.3.2;6.3.2 Hardware at Virtual Prototype Level;209
10.3.3;6.3.3 Hardware--Software Interface at Virtual Prototype Level;209
10.4;6.4 Execution Model of the Virtual Prototype;210
10.5;6.5 Design Space Exploration of Virtual Prototype;211
10.5.1;6.5.1 Goal of Performance Evaluation;211
10.5.2;6.5.2 Architecture/Application Parameters;212
10.5.3;6.5.3 Performance Measurements;212
10.5.4;6.5.4 Design Space Exploration;213
10.6;6.6 Application Examples at the Virtual Prototype Level;214
10.6.1;6.6.1 Motion JPEG Application on Diopsis RDT;214
10.6.2;6.6.2 H.264 Application on Diopsis R2DT;217
10.7;6.7 State of the Art and Research Perspectives;219
10.7.1;6.7.1 State of the Art;219
10.7.2;6.7.2 Research Perspectives;220
10.8;6.8 Conclusions;221
11;7 Conclusions and Future Perspectives;222
11.1;7.1 Conclusions;222
11.2;7.2 Future Perspectives;224
12;Glossary;226
13;References;234
14;Index;242