Reis / Cao / Wirth Circuit Design for Reliability

1. Auflage 2014
ISBN: 978-1-4614-4078-9
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 271 Seiten

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management.

Autoren/Hrsg.

Reis, Ricardo

Cao, Yu

Wirth, Gilson

Inhaltsverzeichnis

1;Contents;6
2;1 Introduction;8
3;2 Recent Trends in Bias Temperature Instability;12
3.1;1 Introduction;12
3.2;2 Brief Overview of BTI;13
3.3;3 Static BTI;13
3.4;4 Dynamic BTI;14
3.5;5 Similarity Between BTI Relaxation and Low-Frequency Noise;15
3.6;6 Semi-quantitative Model for BTI Relaxation;15
3.7;7 Properties of Individual Defects;17
3.8;8 Modeling Properties of Individual Defects;19
3.9;9 BTI Distribution in Deeply-Scaled FETs;21
3.10;10 Technological Solutions;22
3.11;11 Improving PBTI with Rare-Earth Incorporation;23
3.12;12 Improving NBTI in High-Mobility SiGe pFETs;23
3.13;References;25
4;3 Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability;27
4.1;1 Introduction;27
4.2;2 Charge Trapping Events as a Source of Noise;30
4.3;3 Power Spectrum of the RTN Noise due to a Single Trap;31
4.4;4 Approximation for Excitation Frequencies Higher than the Noise Frequency;34
4.5;5 Average Power Spectrum of the RTN Noise due to the Ensemble of Traps;36
4.6;6 Square Wave Excitation;36
4.7;7 Variability in the Power Spectrum of the RTN Noise due to the Ensemble of Traps;39
4.8;8 Experimental Results;41
4.9;9 The Charge Trapping Component of Bias Temperature Instability;42
4.10;References;50
5;4 Atomistic Simulations on Reliability;53
5.1;1 Introduction;53
5.2;2 Discrete Impurity Effects;54
5.2.1;2.1 Some General Considerations;54
5.2.2;2.2 Drift-Diffusion Simulations of Discrete Impurity Effects;54
5.2.3;2.3 Monte Carlo Device Simulations of Discrete Impurity Effects;57
5.3;3 Random Telegraph Signal;61
5.3.1;3.1 Importance of Random Trap Fluctuations;61
5.3.2;3.2 Monte Carlo Device Simulations of Random Traps at the Semiconductor/Oxide Interface;64
5.4;4 Conclusions;68
5.4.1;4.1 Local Surface Potential Fluctuations;69
5.4.2;4.2 Fluctuation in Carrier Mobility;71
5.4.3;4.3 Interface Conditions;71
5.5;References;72
6;5 On-Chip Characterization of Statistical Device Degradation;74
6.1;1 Introduction;74
6.1.1;1.1 Transient Change in Device Parameters;75
6.1.2;1.2 Measurement Requirements;76
6.2;2 Circuit Structures for the Measurement of Device Degradation;77
6.2.1;2.1 Measurements Using Off-Chip Equipment;77
6.2.2;2.2 On-Chip Measurements;78
6.3;3 BTIarray for Statistical Characterization of Device Degradation;79
6.3.1;3.1 Stress and Recovery Time Overlapping;79
6.3.2;3.2 Circuit Structure of BTIarray;81
6.3.3;3.3 Implementation Example;84
6.3.4;3.4 Measurement Automation Through Scripting;85
6.3.5;3.5 Measurement Accuracy;87
6.4;4 Characterization Example of Statistical Degradations;88
6.4.1;4.1 Measurement Scenario;88
6.4.2;4.2 Threshold Voltage Shifts for Small DUTs;90
6.4.3;4.3 Statistical Model Parameter Extraction for NBTI;93
6.4.4;4.4 Measurement Efficiency;95
6.5;5 Chapter Summary;95
6.6;References;96
7;6 Compact Modeling of BTI for Circuit Reliability Analysis;98
7.1;1 Introduction;98
7.1.1;1.1 BTI Aging Models: Challenges and Needs;100
7.2;2 Reliability Physics: Device-Level Modeling of BTI;101
7.2.1;2.1 Static BTI Models;102
7.2.1.1;2.1.1 Reaction: Diffusion Based Static BTI Model;102
7.2.1.2;2.1.2 Trapping/De-trapping Based Static BTI Model;104
7.2.2;2.2 BTI Models Under Random Stress Patterns;106
7.2.2.1;2.2.1 Reaction: Diffusion Based Aging Model for Random Input;107
7.2.2.2;2.2.2 Trapping/De-Trapping Based Random Input Aging Model;110
7.2.3;2.3 Long-Term BTI Model Under DVS;114
7.2.3.1;2.3.1 Long-Term BTI Model Based on Reaction–Diffusion;114
7.2.3.2;2.3.2 Long-Term BTI Model Based on Trapping/De-Trapping;115
7.3;3 Circuit Aging Simulation;117
7.3.1;3.1 Aging Analysis: Digital Circuits;118
7.3.2;3.2 Aging Analysis: AMS Circuits;119
7.4;4 Summary;120
7.5;References;122
8;7 Circuit Resilience Roadmap;125
8.1;1 Introduction;125
8.2;2 Trends in Technology;127
8.2.1;2.1 Manufacturing Variations;127
8.2.2;2.2 Aging;129
8.2.3;2.3 Particle Strikes;130
8.3;3 Trends in Memory;132
8.3.1;3.1 CMOS SRAM;132
8.3.2;3.2 Resilience Key Parameters;134
8.3.3;3.3 Design Trends and Considerations;135
8.3.4;3.4 SRAM Scaling Trends;137
8.4;4 Trends in Logic;139
8.4.1;4.1 Influence of Process Variations;139
8.4.2;4.2 Scaling Trends;142
8.5;5 Conclusion;145
8.6;References;146
9;8 Layout Aware Electromigration Analysis of Power/Ground Networks;148
9.1;1 Introduction to Electromigration;148
9.1.1;1.1 Basic Concepts;148
9.1.2;1.2 Classical Theories;149
9.1.2.1;1.2.1 Black's Equation;149
9.1.2.2;1.2.2 Blech Length Effect;150
9.1.3;1.3 Affecting Factors;151
9.1.3.1;1.3.1 Current Density;151
9.1.3.2;1.3.2 Temperature;152
9.1.3.3;1.3.3 Wire Length;152
9.1.3.4;1.3.4 Interconnect Structure;153
9.1.3.5;1.3.5 Activation Energy;154
9.1.3.6;1.3.6 Diffusion Paths;154
9.2;2 Physical Simulation of EM;155
9.2.1;2.1 Background;155
9.2.2;2.2 Balance of Atom Concentration;156
9.2.3;2.3 Simulation Setup and Result;157
9.3;3 Variation-Aware Compact MTTF Model;157
9.3.1;3.1 Variation Sources;157
9.3.1.1;3.1.1 CMP Dishing;157
9.3.1.2;3.1.2 EPE;158
9.3.2;3.2 Compact Model;159
9.3.2.1;3.2.1 Observations;159
9.3.2.2;3.2.2 Critical Region;160
9.3.2.3;Definition 1;160
9.3.2.4;3.2.3 Compact Model;161
9.4;4 Full-Chip EM Analysis;163
9.4.1;4.1 Power Grid Model;163
9.4.2;4.2 Effective jL Product Extraction;164
9.4.3;4.3 Analytical Lifetime Calculation;165
9.4.4;4.4 Global Current Redistribution;167
9.4.5;4.5 VEMA Flow;168
9.5;5 Experimental Results;169
9.5.1;Definition 2;173
9.6;References;175
10;9 Power-Gating for Leakage Control and Beyond;177
10.1;1 Introduction;178
10.2;2 Design Issues for Nanometric CMOS Circuits;179
10.2.1;2.1 Sub-threshold Leakage Power Consumption;179
10.2.2;2.2 Sources of Variability;180
10.3;3 Power-Gating for Leakage Power Reduction;182
10.3.1;3.1 Power-Gating Basics;182
10.3.2;3.2 Clustered Row-Based Sleep Transistor Insertion Methodology;184
10.3.2.1;3.2.1 Peak Current Estimation;185
10.3.2.2;3.2.2 Sleep Transistor Sizing;186
10.3.2.3;3.2.3 Power-Gating Strategies;188
10.3.2.4;3.2.4 Layout Modification;188
10.4;4 Clustered Tunable Power-Gating for PV Compensation;190
10.4.1;4.1 Modeling Process Variations and Timing Yield;190
10.4.2;4.2 Controlling Performance with Tunable Sleep-Transistors;191
10.4.3;4.3 Design Issues and Architectures;193
10.4.3.1;4.3.1 Design Issues;193
10.4.3.2;4.3.2 Architectures;193
10.4.3.3;4.3.3 Design Flow and Results;194
10.5;5 Clustered Power-Gating for NBTI-Induced Aging Minimization;196
10.5.1;5.1 Background and Models;197
10.5.2;5.2 Power-Gating and Aging Reduction;199
10.5.3;5.3 Design Issues and Architectures;200
10.5.3.1;5.3.1 Design Issues;200
10.5.3.2;5.3.2 Architectures;202
10.5.3.3;5.3.3 Design Flow and Results;203
10.6;References;205
11;10 Soft Error Rate and Fault Tolerance Techniques for FPGAs;208
11.1;1 Introduction;208
11.2;2 FPGAs Under Soft Errors;209
11.2.1;2.1 Single Event Effects on SRAM-Based FPGAs;210
11.2.2;2.2 Single Event Effects on Flash-Based FPGAs;210
11.2.3;2.3 Single Event Effects on Antifuse-Based FPGAs;212
11.3;3 Fault Tolerance Techniques for FPGAs;213
11.3.1;3.1 SRAM-Based FPGAs;214
11.3.2;3.2 FLASH-Based and Antifuse-Based FPGAs;218
11.4;4 Radiation Test Methodologies to Predict and Measure SER in FPGAs;218
11.5;References;221
12;11 Low Power Robust FinFET-Based SRAM Design in Scaled Technologies;223
12.1;1 Introduction;223
12.1.1;1.1 Alternate Device Structures;224
12.1.2;1.2 Fundamentals of FinFETs;225
12.1.3;1.3 Fundamentals of 6 T SRAMs;226
12.2;2 Co-optimization of Fin Ratio and Fin Thickness;227
12.3;3 Joint Optimization of Fin Height, Fin Thickness, Oxide Thickness, Supply Voltage and Threshold Voltage;230
12.4;4 Fin Rotation and Orientation;233
12.5;5 Spacer Thickness Optimization;235
12.5.1;5.1 Symmetric Spacer Optimization;235
12.5.2;5.2 Asymmetric Drain Spacer Extension FinFETs;237
12.6;6 SRAMs based on Asymmetrically Doped (AD) FinFETs;240
12.7;7 Independent Gate FinFETs;242
12.7.1;7.1 Bi-mode Independent Gate FinFET SRAMs;243
12.7.2;7.2 Tri-Mode Independent Gate FinFET SRAMs;246
12.7.3;7.3 Pass Gate Feedback in FinFET SRAMs;249
12.8;8 Summary;251
12.9;References;252
13;12 Variability-Aware Clock Design;254
13.1;1 Introduction;254
13.1.1;1.1 Definitions;256
13.1.2;1.2 Robustness;256
13.2;2 Variability;257
13.2.1;2.1 Types of Variation;257
13.2.1.1;2.1.1 Process;258
13.2.1.2;2.1.2 Voltage;258
13.2.1.3;2.1.3 Temperature;258
13.2.1.4;2.1.4 Crosstalk;259
13.2.2;2.2 Impact of Variation Models;259
13.2.3;2.3 Common Industry Models;261
13.2.4;2.4 Requirements for Variation Models;261
13.2.5;2.5 Analysis Methodologies;262
13.3;3 Clock Trees;263
13.4;4 Clock Meshes;266
13.5;References;269