Sachdev / Pineda de Gyvez Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

2. Auflage 2007
ISBN: 978-0-387-46547-0
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 34, 328 Seiten

Reihe: Frontiers in Electronic Testing

The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

Autoren/Hrsg.

Sachdev, Manoj

Pineda de Gyvez, José

Inhaltsverzeichnis

1;Dedication;6
2;Contents;7
3;Preface;12
4;Foreword;15
5;Foreword for the First Edition;17
6;Acknowledgements;19
7;Chapter 1 INTRODUCTION;20
7.1;1. EVOLUTION OF CMOS TECHNOLOGY;20
7.2;2. THE TEST COMPLEXITY;24
7.3;3. QUALITY AND RELIABILITY AWARENESS;28
7.4;4. BUILDING QUALITY AND RELIABILITY;30
7.5;5. OBJECTIVES OF THIS BOOK;34
7.6;6. BOOK ORGANIZATION;35
7.7;References;37
8;Chapter 2 FUNCTIONAL AND PARAMETRIC DEFECT MODELS;42
8.1;1. BRIEF CLASSIFICATION OF DEFECTS;42
8.1.1;1.1 Defect-Fault Relationship;45
8.2;2. INDUCTIVE FAULT ANALYSIS;47
8.2.1;2.1 IC Design and Layout Related Defect Sensitivity;48
8.2.2;2.2 Defect Sensitive Design;48
8.2.3;2.3 Basic Concepts of IFA;49
8.3;3. PARAMETRIC DEFECT AND FAULT MODELS;51
8.3.1;3.1 Threshold Voltage Mismatch (.Vt) Fault Modeling;51
8.3.2;3.2 Sources of Threshold Voltage Variability;52
8.3.3;3.3 Leakage Current due to Vt Mismatch Mismatch;53
8.3.4;3.4 Delay in Parallel-connected Networks;58
8.3.5;3.5 Delay Variation Model with with for Parallel Transistor Networks;60
8.3.6;3.6 Spot Defect Statistics: Resistive Opens;64
8.4;4. FUNCTIONAL DEFECT MODELS;69
8.4.1;4.1 Critical Areas;72
8.4.2;4.2 Defect Statistics;73
8.4.3;4.3 Average Probability of Failure of Long Interconnects;77
8.4.4;4.4 Average Critical Area of N Conductors;80
8.5;5. CONCLUSIONS;83
8.6;References;83
9;Chapter 3 DIGITAL CMOS FAULT MODELING;87
9.1;1. OBJECTIVES OF FAULT MODELING;87
9.2;2. LEVELS OF TESTING;89
9.3;3. LEVELS OF FAULT MODELING;91
9.3.1;3.1 Logic Level Fault Modeling;91
9.3.2;3.2 Transistor Level Fault Modeling;99
9.3.3;3.3 Layout Level Fault Modeling;108
9.3.4;3.4 Function Level Fault Modeling;109
9.3.5;3.5 Delay Fault Models;110
9.3.6;3.6 Leakage Fault Model;115
9.3.7;3.7 Temporary Faults;116
9.4;4. CONCLUSIONS;120
9.5;References;120
10;Chapter 4 DEFECTS IN LOGIC CIRCUITS AND THEIR TEST IMPLICATIONS;129
10.1;1. INTRODUCTION;129
10.2;2. STUCK-AT FAULTS AND MANUFACTURING DEFECTS;131
10.2.1;2.1 Study by Galiay, Crouzet, and Vergniault;132
10.2.2;2.2 Study by Banerjee and Abraham;133
10.2.3;2.3 Study by Maly, Ferguson and Shen;138
10.2.4;2.4 Gate Oxide Shorts: Study by Hawkins and Soden;141
10.3;3. IFA EXPERIMENTS ON STANDARD CELLS;144
10.4;4. IDDQ VERSUS VOLTAGE TESTING;148
10.5;5. DEFECTS IN SEQUENTIAL CIRCUITS;151
10.5.1;5.1 Undetected Defects;153
10.5.2;5.2 Defect Detection Technique;155
10.5.3;5.3 IDDQ Testable Flip- flop;157
10.5.4;5.4 Defects and Scan Chains;157
10.6;6. DEFECT CLASSES AND THEIR TESTING;161
10.7;7. APPLICATION OF IFA IN NANO-METRIC TECHNOLOGIES;161
10.8;8. CONCLUSIONS;164
10.9;References;165
11;Chapter 5 TESTING DEFECTS AND PARAMETRIC VARIATIONS IN RAMS;169
11.1;1. INTRODUCTION;169
11.2;2. TRADITIONAL RAM FAULT MODELS;171
11.2.1;2.1 Stuck-at Fault Model;171
11.2.2;2.2 Coupling Fault Model;172
11.2.3;2.3 Pattern Sensitivity Fault Model;172
11.3;3. DEFECT BASED RAM FAULT MODEL DEVELOPMENT;173
11.3.1;3.1 Defect based SRAM Fault Models and Test Algorithms;173
11.3.2;3.2 Subsequent Defect-oriented SRAM Test Development;178
11.3.3;3.3 Defect based DRAM Fault Models and Test Algorithms;181
11.3.4;3.4 TCAM Fault Models and Test Algorithms;194
11.4;4. ADDRESS DECODER DEFECTS;203
11.4.1;4.1 Early Work on Address Decoder Faults;205
11.4.2;4.2 Technological Differences;205
11.4.3;4.3 Failure and Analysis;207
11.4.4;4.4 Why Non-detection by March Tests?;210
11.4.5;4.5 Address Decoder Open Defects;211
11.4.6;4.6 Supplementary Test Algorithm;213
11.4.7;4.7 Testability Techniques for Decoder Open Defects;215
11.4.8;4.8 Recent Work on Address Decoder Defects;218
11.5;5. PARAMETRIC TESTING OF SRAMS;218
11.5.1;5.1 SRAM Cell and SNM;221
11.5.2;5.2 Process Variation and SNM;225
11.5.3;5.3 Manufacturing Defects and SNM;227
11.5.4;5.4 Weak Cell Fault Model;228
11.5.5;5.5 DFT Techniques to Detect Weak Cells;229
11.6;6. IDDQ BASED RAM TESTING;233
11.7;7. CONCLUSIONS;233
11.8;References;235
12;Chapter 6 DEFECT- ORIENTED ANALOG TESTING;242
12.1;1. INTRODUCTION;243
12.2;2. ANALOG TEST COMPLEXITY;244
12.3;3. PREVIOUS WORK;245
12.3.1;3.1 Estimation Method;245
12.3.2;3.2 Topological Method;245
12.3.3;3.3 Taxonomical Method;247
12.4;4. DEFECT BASED REALISTIC FAULT DICTIONARY;247
12.4.1;4.1 Implementation;251
12.5;5. A CASE STUDY;257
12.5.1;5.1 Fault Matrix Generation;257
12.5.2;5.2 Stimuli Matrix;259
12.5.3;5.3 Simulation Results;260
12.5.4;5.4 Silicon Results;261
12.5.5;5.5 Observations and Analysis;265
12.5.6;5.6 IFA: Strengths and Weaknesses;266
12.6;6. INPUT STIMULI GENERATION;268
12.6.1;6.1 Power Supply Ramp Input Test Stimuli;269
12.6.2;6.2 Amplifier Specs;271
12.6.3;6.3 Structural vs. Functional Fault Coverage;276
12.6.4;6.4 Experimental Results;281
12.7;7. IFA BASED FAULT GRADING AND DfT FOR ANALOG CIRCUITS;285
12.7.1;7.1 A/D Converter Testing;285
12.7.2;7.2 Description of the Experiment;286
12.7.3;7.3 Fault Simulation Issues;287
12.7.4;7.4 Fault Simulation Results;289
12.8;8. HIGH LEVEL ANALOG FAULT MODELS;295
12.9;9. CONCLUSIONS;298
12.10;References;301
13;Chapter 7 YIELD ENGINEERING;305
13.1;1. MATHEMATICAL MODELS FOR YIELD PREDICTION;305
13.1.1;1.1 Layout Oriented Yield Prediction;316
13.2;2. YIELD ENGINEERING;317
13.3;3. ECONOMICS AND YIELD FORECASTING;322
13.4;4. CONCLUSIONS;328
13.5;References;329
14;Chapter 8 CONCLUSION;332
14.1;1. TEST AND YIELD ENGINEERING COMPLEXITY IN NANO- METRIC TECHNOLOGIES;332
14.2;2. ROLE OF DEFECT-ORIENTED TESTING;335
14.2.1;2.1 Strengths of Defect-oriented Testing;335
14.2.2;2.2 Limitations of Defect-oriented Testing;336
14.3;3. FUTURE DIRECTIONS;336
14.4;References;338
15;Index;340