Sutherland / Mills Verilog and SystemVerilog Gotchas

101 Common Coding Errors and How to Avoid Them
1. Auflage 2010
ISBN: 978-0-387-71715-9
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 218 Seiten

This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.

Autoren/Hrsg.

Sutherland, Stuart

Mills, Don

Inhaltsverzeichnis

1;Dedication;5
2;About the Authors;6
3;Acknowledgments;7
4;Table of Contents;8
5;List of Gotchas;12
6;Foreword by Steve Golson;20
7;Chapter 1 Introduction, What Is A Gotcha?;22
7.1;What are Verilog and System Verilog?;22
7.2;What is a Gotcha?;23
7.3;The Verilog and System Verilog standards;24
8;Chapter 2 Declaration and Literal Number Gotchas;26
8.1;Gotcha 1: Case sensitivity;26
8.2;Gotcha 2: Implicit net declarations;29
8.3;Gotcba 3: Default of 1-bit internal nets;32
8.4;Gotcha 4: Single file versus multi-file compilation of $unit declarations;34
8.5;Gotcha 5: Local variable declarations;36
8.6;Gotcha 6: Escaped names in hierarchical paths;38
8.7;Gotcha 7: Hierarchical references to automatic variables;41
8.8;Gotcha 8: Hierarchical references to variables in unnamed blocks;44
8.9;Gotcha 9: Hierarchical references to imported package items;46
8.10;Gotcha 10: Importing enumerated types from packages;47
8.11;Gotcha 11: Importing from multiple packages;48
8.12;Gotcha 12: Default base of literal integers;49
8.13;Gotcha 13: Signedness of literal integers;51
8.14;Gotcha 14: Signed literal integers zero extend to their specified size;52
8.15;Gotcha 15: Literal integersize mismatch in assignments;54
8.16;Gotcha 16: Filling vectors with all ones;56
8.17;Gotcha 17: Array literals versus concatenations;57
8.18;Gotcha 18: Port connection rules;58
8.19;Gotcha 19: Back-driven ports;62
8.20;Gotcha 20: Passing real (floating point) numbers through ports;65
9;Chapter 3 RTL Modeling Gotchas;67
9.1;Gotcha 21: Combinational logic sensitivity lists with function calls;67
9.2;Gotcha 22: Arrays in sensitivity lists;70
9.3;Gotcha 23: Vectors in sequential logic sensitivity lists;72
9.4;Gotcha 24: Operations in sensitivity lists;74
9.5;Gotcha 25: Sequential logic blocks with begin...end groups;75
9.6;Gotcha 26: Sequential logic blocks with resets;77
9.7;Gotcha 27: Asynchronous set/reset flip-flop for simulation and synthesis;78
9.8;Gotcha 28: Blocking assignments in sequential procedural blocks;80
9.9;Gotcha 29: Sequential logic that requires blocking assignments;82
9.10;Gotcha 30: Nonblocking assignments in combinational logic;84
9.11;Gotcha 31: Combinational logic assignments in the wrong order;88
9.12;Gotcha 32: Casez/casex masks in case expressions;90
9.13;Gotcha 33: Incomplete decision statements;92
9.14;Gotcha 34: Overlapped decision statements;95
9.15;Gotcha 35: Inappropriate use of unique case statements;97
9.16;Gotcha 36: Resetting 2-state models;100
9.17;Gotcha 37: Locked state machines modeled with enumerated types;102
9.18;Gotcha 38: Hidden design problems with 4-state logic;104
9.19;Gotcha 39: Hidden design problems using 2-state types;106
9.20;Gotcha 40: Hidden problems with out-or-bounds array access;108
9.21;Gotcha 41: Out-or-bounds assignments to enumerated types;110
9.22;Gotcha 42: Undetected shared variables in modules;112
9.23;Gotcha 43: Undetected shared variables in interfaces and packages;114
10;Chapter 4 Operator Gotchas;116
10.1;Gotcha 44: Assignments in expressions;116
10.2;Gotcha 45: Self-determined versus context-determined operators;118
10.3;Gotcha 46: Operation size and sign extension in assignment statements;122
10.4;Gotcha 47: Signed arithmetic rules;125
10.5;Gotcha 48: Bit-select and part-select operations;128
10.6;Gotcha 49: Increment, decrement and assignment operators;129
10.7;Gotcha 50: Pre-increment versus post-increment operations;130
10.8;Gotcha 51: Modifying a variable multiple times in onestatement;132
10.9;Gotcha 52: Operator evaluation short circuiting;133
10.10;Gotcha 53: The not operator ( ! ) versus the invert operator ( ~ );135
10.11;Gotcha 54: Array method operations;136
10.12;Gotcha 55: Array method operations on an array subset;138
11;Chapter 5 General Programming Gotchas;139
11.1;Gotcha 56: Verifying asynchronous and synchronous reset at time zero;139
11.2;Gotcha 57: Nested if ...else blocks;144
11.3;Gotcha 58: Evaluation of equality with 4-state values;145
11.4;Gotcha 59: Event trigger race conditions;147
11.5;Gotcha 60: Using semaphores for synchronization;150
11.6;Gotcha 61: Using mailboxes for synchronization;153
11.7;Gotcha 62: Triggering on clocking blocks;155
11.8;Gotcha 63: Misplaced semicolons after decision statements;156
11.9;Gotcha 64: Misplaced semicolons in for loops;158
11.10;Gotcha 65: Infinite for loops;160
11.11;Gotcha 66: Locked simulation due to concurrent for loops;161
11.12;Gotcha 67: Referencing for loop control variables;163
11.13;Gotcha 68: Default function return size;164
11.14;Gotcha 69: Task/function arguments with default values;166
11.15;Gotcha 70: Continuous assignments with delays cancel glitches;167
12;Chapter 6 Object Oriented and Multi-Threaded Programming Gotchas;169
12.1;Gotcha 71: Programming statements in a class;169
12.2;Gotcha 72: Using interfaces with object-oriented testbenches;171
12.3;Gotcha 73: All objects in mailbox come out with the same values;173
12.4;Gotcha 74: Passing handles to methods using input versus ref arguments;174
12.5;Gotcha 75: Constructing an array of objects;175
12.6;Gotcha 76: Static tasks and functions are not re-entrant;176
12.7;Gotcha 77: Static versus automatic variable initialization;178
12.8;Gotcha 78: Forked programming threads need automatic variables;180
12.9;Gotcha 79: Disable fork kills too many threads;182
12.10;Gotcha 80: Disabling a statement block stops more than intended;184
12.11;Gotcha 81: Simulation exits prematurely, before tests complete;187
13;Chapter 7 Randomization, Coverage and Assertion Gotchas;189
13.1;Gotcha 82: Variables declared with rand are not getting randomized;189
13.2;Gotcha 83: Undetected randomization failures;191
13.3;Gotcha 84: $assertoff could disable randomization;193
13.4;Gotcha 85: Boolean constraints on more than two random variables;195
13.5;Gotcha 86: Unwanted negative values in random values;197
13.6;Gotcha 87: Coverage reports default to groups, not bins;198
13.7;Gotcha 88: Coverage is always reported as 0%;200
13.8;Gotcha 89: The coverage report lumps all instances together;202
13.9;Gotcha 90: Covergroup argument directions are sticky;203
13.10;Gotcha 91: Assertion pass statements execute with a vacuous success;204
13.11;Gotcha 92: Concurrent assertions in procedural blocks;206
13.12;Gotcha 93: Mismatch in assert...else statements;208
13.13;Gotcha 94: Assertions that cannot fail;209
14;Chapter 8 Tool Compatibility Gotchas;211
14.1;Gotcha 95: Default simulation time units and precision;211
14.2;Gotcha 96: Package chaining;214
14.3;Gotcha 97: Random number generator is not consistent across tools;216
14.4;Gotcha 98: Loading memories modeled with aIways_latch/always_ff;218
14.5;Gotcha 99: Non-standard language extensions;220
14.6;Gotcha 100: Array literals versus concatenations;222
14.7;Gotcha 101: Module ports that pass floating point values (real types);224
15;Index;225

Leseproben

"Foreword by Steve Golson (p. 1-2)

Some people collectbaseball cards, old car magazines, or maybe rubber duckies. I collectVerilog books. It started back in 1989 with a looseleaf copy of "Gateway VERILOG-XL Reference Manual Version I.5a" in a three-ring binder. Verilog was a bit simpler back then-its hard to believe we actually designed chipsusing onlyone typeof procedural assignment (nonblocking assigns were not part of the language yet). Andwe ran our simulations on a VAX, or maybe a fancy Apollo workstation.

Sincethen Ive bought prettymuchevery Verilog bookthatcamealong. Ive got a few synthesis books, and Ill pick up an occasional VHDL reference or maybe a text on the history of hardware description languages, but mostly its Verilog. Dozens and dozens of booksabout Verilog. Theresa funny thingaboutmostof these books though.

AfterI leaf through them a few times, they sit on the shelf. I admitthat it looks pretty impressive onceyou have an entire bookcase filled with Verilog books, but the discerning visitor will notice howfresh andnewthey all are. Unused. Unread. Useless. Im often disappointed to find very little information which is useful for the practicing engineer. What Im looking for is a book I can use every day, a book that will helpme getmy chip out the door, on timeand working. StuandDonhavewritten sucha book.

Ive known these guysformanyyears, and they have probably forgotten more Verilog than Ive ever known. They have distilled their collective knowledge into this helpful and extremely useful book. Readit and you wontbe disappointed. If you are an old hand at Verilog try to pick out all the Gotchas that you have found the hard way. Smile and say to yourself "Oh yeah, I remember getting caught by that one!"

Those of you who are new to Verilog and SystemVerilog, welcome aboard! Heres your chance to learn from two of the leading experts in the field. And if you ever have a chance to take a training class from either of these gentlemen, donthesitate to signup. I guarantee you wont regretit. Ohby the way, myfavorite Gotcha is "Gotcha 65: Infinite for loops". Why? Well, I builta chipwiththatbug in it. Believe me,when a modeling errorcauses youto have broken silicon, you never forget why it happened. Back then I didnt have this book to help me, but you do! Keep this book close at hand, refer to it often, andmayall yourmodels compile andall yourloops terminate.

Steve Golson
Trilobyte Systems
http://www.trilobyte.com"