Sutherland / Mills Verilog and SystemVerilog Gotchas

101 Common Coding Errors and How to Avoid Them
1. Auflage 2010
ISBN: 978-0-387-71715-9
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 218 Seiten, Web PDF

Reihe: Engineering

In programming, “Gotcha” is a well known term. A gotcha is a language feature, which, if misused, causes unexpected - and, in hardware design, potentially disastrous - behavior. The purpose of this book is to enable engineers to write better Verilog/SystemVerilog design and verification code, and to deliver digital designs to market more quickly.

This book shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize these common coding mistakes, and know how to avoid them. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug the errors.

This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Sutherland, Stuart

Mills, Don

Inhaltsverzeichnis

Introduction, What Is A Gotcha?.- Declaration and Literal Number Gotchas.- RTL Modeling Gotchas.- Operator Gotchas.- General Programming Gotchas.- Object Oriented and Multi-Threaded Programming Gotchas.- Randomization, Coverage and Assertion Gotchas.- Tool Compatibility Gotchas.

Leseproben

"Foreword by Steve Golson (p. 1-2)

Some people collectbaseball cards, old car magazines, or maybe rubber duckies. I collectVerilog books. It started back in 1989 with a looseleaf copy of "Gateway VERILOG-XL Reference Manual Version I.5a" in a three-ring binder. Verilog was a bit simpler back then-its hard to believe we actually designed chipsusing onlyone typeof procedural assignment (nonblocking assigns were not part of the language yet). Andwe ran our simulations on a VAX, or maybe a fancy Apollo workstation.

Sincethen Ive bought prettymuchevery Verilog bookthatcamealong. Ive got a few synthesis books, and Ill pick up an occasional VHDL reference or maybe a text on the history of hardware description languages, but mostly its Verilog. Dozens and dozens of booksabout Verilog. Theresa funny thingaboutmostof these books though.

AfterI leaf through them a few times, they sit on the shelf. I admitthat it looks pretty impressive onceyou have an entire bookcase filled with Verilog books, but the discerning visitor will notice howfresh andnewthey all are. Unused. Unread. Useless. Im often disappointed to find very little information which is useful for the practicing engineer. What Im looking for is a book I can use every day, a book that will helpme getmy chip out the door, on timeand working. StuandDonhavewritten sucha book.

Ive known these guysformanyyears, and they have probably forgotten more Verilog than Ive ever known. They have distilled their collective knowledge into this helpful and extremely useful book. Readit and you wontbe disappointed. If you are an old hand at Verilog try to pick out all the Gotchas that you have found the hard way. Smile and say to yourself "Oh yeah, I remember getting caught by that one!"

Those of you who are new to Verilog and SystemVerilog, welcome aboard! Heres your chance to learn from two of the leading experts in the field. And if you ever have a chance to take a training class from either of these gentlemen, donthesitate to signup. I guarantee you wont regretit. Ohby the way, myfavorite Gotcha is "Gotcha 65: Infinite for loops". Why? Well, I builta chipwiththatbug in it. Believe me,when a modeling errorcauses youto have broken silicon, you never forget why it happened. Back then I didnt have this book to help me, but you do! Keep this book close at hand, refer to it often, andmayall yourmodels compile andall yourloops terminate.

Steve Golson
Trilobyte Systems
http://www.trilobyte.com"