Tuma / Buermen Circuit Simulation with SPICE OPUS

Theory and Practice
1. Auflage 2009
ISBN: 978-0-8176-4867-1
Verlag: Birkhäuser Basel
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 399 Seiten

This book is the first complete guide to analog circuit design using the circuit simulator software package SPICE OPUS. Developed by the authors and used by academics and industry professionals worldwide, SPICE OPUS is an improved version of the well-known University of California at Berkeley circuit simulator SPICE3 that has been freely available online since 2000.

Aimed at novices as well as professional circuit designers, the book is a unique combination of a basic guide to general analog circuit simulation and a SPICE OPUS software manual. All simulations as well as the free simulator software may be directly downloaded from the SPICE OPUS homepage: www.spiceopus.si. The book is divided into three parts: mathematical theory of circuit analysis, a crash course in SPICE OPUS, and a complete SPICE OPUS reference guide.

Circuit Simulation with SPICE OPUS is intended for a wide audience of undergraduate and graduate students, researchers, and practitioners in electrical and systems engineering, circuit design, and simulation development. The book may be used as a textbook for an advanced undergraduate or graduate course on circuit simulation as well as a self-study reference guide for students and researchers alike.

Autoren/Hrsg.

Tuma, Tadej

Buermen, Árpád

Inhaltsverzeichnis

1;Contents;6
2;Abbreviations;12
3;About SPICE OPUS and This Book;14
4;Introduction to Circuit Simulation;16
4.1;1.1 Signals and Linear Systems;16
4.2;1.2 Lumped Circuits;18
4.3;1.3 DC Solutions and the Operating Point of a Circuit;25
4.4;1.4 Incremental DC Circuit Model;28
4.5;1.5 Circuit’s Response in the Time Domain;33
4.6;1.6 Fourier Series and Fourier Transformation;35
4.7;1.7 Incremental Circuit Model in the Time Domain;37
4.8;1.8 Incremental Circuit Model in the Frequency Domain;40
4.9;1.9 Noise Signals in LTI Systems;42
4.10;1.10 Circuit Noise Modeling and Analysis;44
4.11;1.11 Laplace Transformation and the s-Domain;47
4.12;1.12 Circuit Analysis in the s-Domain, DC Solution Stability;48
5;Short Tutorial;51
5.1;2.1 Installation;51
5.2;2.2 Starting SPICE OPUS;52
5.3;2.3 The Command Window;54
5.4;2.4 Describing a Circuit;55
5.5;2.5 Operating Point (OP) Analysis;59
5.6;2.6 Operating Point Sweep (DC), Plotting of Simulation Results;62
5.7;2.7 Small Signal Analysis (AC and TF);67
5.8;2.8 Pole-Zero Analysis (PZ);75
5.9;2.9 Small Signal Noise Analysis (NOISE);79
5.10;2.10 Time-Domain Analysis (TRAN);85
5.11;2.11 Interactive Interpreter and Advanced Features;90
6;Input File Syntax;103
6.1;3.1 File Structure;103
6.2;3.2 Numbers;104
6.3;3.3 Instances and Nodes;104
6.4;3.4 Models;105
6.5;3.5 Instance and Model Parameters;106
6.6;3.6 Device Syntax;107
6.7;3.7 Binning of MOS Models;162
6.8;3.8 Including Files in the Netlist;166
6.9;3.9 Describing Circuits Hierarchically;167
6.10;3.10 Initial Operating Point Solution and Initial Conditions;171
6.11;3.11 Joining Multiple Topologies in a Netlist;172
6.12;3.12 Simulator Parameters;173
7;Analyzing the Circuit;177
7.1;4.1 Operating Point (OP) Analysis;177
7.2;4.2 Operating Point Sweep Analysis (DC Analysis);181
7.3;4.3 DC Transfer Function Analysis (TF Analysis);183
7.4;4.4 Small Signal Analysis (AC Analysis);184
7.5;4.5 Pole-Zero (PZ) Analysis;185
7.6;4.6 Noise (NOISE) Analysis;186
7.7;4.7 Transient (TRAN) Analysis;187
8;NUTMEG Scripting Language;190
8.1;5.1 Input Handling;190
8.2;5.2 Text Output;196
8.3;5.3 Plots, Vectors, and Expressions;196
8.4;5.4 Variables;211
8.5;5.5 Circuits;216
8.6;5.6 Simulation;228
8.7;5.7 Analyzing the Results;237
8.8;5.8 Plotting the Results;246
8.9;5.9 Control Structures;263
8.10;5.10 Miscellaneous;265
9;Mathematical Background;269
9.1;6.1 Linear Resistive Networks;269
9.2;6.2 Solving the Set of Circuit Equations;278
9.3;6.3 Introducing Nonlinear Devices;286
9.4;6.4 Dynamic Devices and Frequency-Domain Analysis;307
9.5;6.5 Transient (Time-Domain) Analysis (TRAN);315
10;Examples;340
10.1;7.1 Parametrized Attenuator and Transmission Lines;340
10.2;7.2 Modeling a Nonlinear Transformer;346
10.3;7.3 Analyzing a CMOS Differential Amplifier;352
10.4;7.4 Using Corner Models;361
10.5;7.5 Local Variations (Mismatch) and Monte-Carlo Analysis;368
10.6;7.6 Drawing Histograms, Yield Analysis;373
10.7;7.7 Logic Gates;375
10.8;7.8 Flip-Flops;378
10.9;7.9 Counters and Frequency Dividers;382
10.10;7.10 Phase Frequency Detector;384
10.11;7.11 Voltage-Controlled Oscillator;389
10.12;7.12 Phase-Locked Loop;392
11;References;397
12;Index;400