Zhang Embedded Memories for Nano-Scale VLSIs

1. Auflage 2009
ISBN: 978-0-387-88497-4
Verlag: Springer-Verlag
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 400 Seiten

Kevin Zhang Advancement of semiconductor technology has driven the rapid growth of very large scale integrated (VLSI) systems for increasingly broad applications, incl- ing high-end and mobile computing, consumer electronics such as 3D gaming, multi-function or smart phone, and various set-top players and ubiquitous sensor and medical devices. To meet the increasing demand for higher performance and lower power consumption in many different system applications, it is often required to have a large amount of on-die or embedded memory to support the need of data bandwidth in a system. The varieties of embedded memory in a given system have alsobecome increasingly more complex, ranging fromstatictodynamic and volatile to nonvolatile. Among embedded memories, six-transistor (6T)-based static random access memory (SRAM) continues to play a pivotal role in nearly all VLSI systems due to its superior speed and full compatibility with logic process technology. But as the technology scaling continues, SRAM design is facing severe challenge in mainta- ing suf?cient cell stability margin under relentless area scaling. Meanwhile, rapid expansion in mobile application, including new emerging application in sensor and medical devices, requires far more aggressive voltage scaling to meet very str- gent power constraint. Many innovative circuit topologies and techniques have been extensively explored in recent years to address these challenges.

Autoren/Hrsg.

Zhang, Kevin

Inhaltsverzeichnis

1;Contents;6
2;Contributors;7
3;to 1 Introduction;8
3.1;1.1 Chapter 2: Embedded Memory Architecture for Low-Power Application Processor, by Hoi Jun Yoo;10
3.2;1.2 Chapter 3: Embedded SRAM Design in Nanometer-Scale Technologies, by Hiroyuki Yamauchi;11
3.3;1.3 Chapter 4: Ultra Low Voltage SRAM Design, by Naveen Verma and Anantha P. Chandrakasan;11
3.4;1.4 Chapter 5: Embedded DRAM in Nano-Scale Technologies, by John Barth;11
3.5;1.5 Chapter 6: Embedded Flash Memory, by Hideto Hidaka;11
3.6;1.6 Chapter 7: Embedded Magnetic RAM, by Hideto Hidaka;11
3.7;1.7 Chapter 8: FeRAM, by Shoichiro Kawashima and Jeffrey S. Cross;12
3.8;1.8 Chapter 9: Statistical Blockade: Estimating Rare Event Statistics for Memories, by Amith Singhee and Rob A. Rutenbar;12
4;to 2 Embedded Memory Architecture for Low-Power Application Processor;13
4.1;2.1 Memory Hierarchy;13
4.1.1;2.1.1 Introduction;13
4.1.2;2.1.2 Advantages of the Memory Hierarchy;14
4.1.3;2.1.3 Components of the Memory Hierarchy;15
4.1.3.1;2.1.3.1 Register File;15
4.1.3.2;2.1.3.2 Cache;16
4.1.3.3;2.1.3.3 Scratch Pad Memory;16
4.1.3.4;2.1.3.4 Off-Chip RAMs;16
4.1.3.5;2.1.3.5 Mass Storages;17
4.2;2.2 Memory Access Pattern Related Techniques;17
4.2.1;2.2.1 Bank Interleaving;17
4.2.2;2.2.2 Address Alignment Logic in KAIST RAMP-IV;20
4.2.3;2.2.3 Read--Modify--Write (RMW) DRAM;21
4.3;2.3 Embedded Memory Architecture Case Studies;22
4.3.1;2.3.1 PXA300 Processor;22
4.3.2;2.3.2 Imagine;24
4.3.3;2.3.3 Memory-Centric NoC;26
4.3.3.1;2.3.3.1 SIFT Algorithm;27
4.3.3.2;2.3.3.2 Architecture of the Memory-Centric NoC;29
4.3.3.3;2.3.3.3 Memory-Centric NoC Operation;30
4.4;2.4 Low-Power Embedded Memory Design;33
4.4.1;2.4.1 General Low-Power Techniques;33
4.4.2;2.4.2 Embedded DRAM Design in RAMP-IV;35
4.4.3;2.4.3 Combination of Processing Units and Memory -- Visual Image Processing Memory;38
5;to 3 Embedded SRAM Design in Nanometer-Scale Technologies;45
5.1;3.1 Introduction;45
5.1.1;3.1.1 Embedded SRAMs in VLSI Chip;46
5.1.2;3.1.2 SRAM Cells Array Configuration;47
5.1.2.1;3.1.2.1 Six Transistor SRAM Cell;48
5.1.2.2;3.1.2.2 SRAM Read;48
5.1.2.3;3.1.2.3 SRAM Write;49
5.1.2.4;3.1.2.4 SRAM Data Retention;50
5.1.3;3.1.3 SRAM Cell Scaling Trend;50
5.1.4;3.1.4 SRAM-Operating Voltage V DD Scaling Trend;52
5.2;3.2 Functional Margin Issues with Scaled Nanometer-Scale SRAM;52
5.2.1;3.2.1 Static Noise Margin (SNM);52
5.2.2;3.2.2 Write Margin (WRM);54
5.2.3;3.2.3 Cell Current (Icell) Distribution;54
5.2.4;3.2.4 V DD Scaling and SRAM Functionality;55
5.2.5;3.2.5 Device Feature Size Dependency of Functional Margins;56
5.3;3.3 Cell Stability Improvement;58
5.3.1;3.3.1 Read and Write Margin Assist Circuits;59
5.3.1.1;3.3.1.1 Read Margin Assist and Its Limitation;59
5.3.1.2;3.3.1.2 Write Margin Assist and Its Limitation;62
5.3.1.3;3.3.1.3 Body Biasing Scheme for Read and Write Assists and Its Limitation;65
5.3.1.4;3.3.1.4 Dynamic vs Static Read and Write Cell Stabilities;66
5.3.1.5;3.3.1.5 SRAM-Designated Power Supply Scheme;66
5.3.2;3.3.2 SRAM with Multiple Power Supplies Against Single-Rail Scheme;67
5.4;3.4 New Cell Topology to Improve Read and Write Stabilities;70
5.4.1;3.4.1 8T SRAM;71
5.4.2;3.4.2 10T SRAM;72
5.5;3.5 Read and Write Multiplexing;73
5.5.1;3.5.1 Pulsed Word-Line and Bit-Line Scheme;74
5.5.2;3.5.2 Time Division for Read with Suppressed WL and Write Operation;75
5.5.3;3.5.3 Time Division for Read with Decoupled Read Port and Write Operation;75
5.6;3.6 Analysis on SRAM Design Solutions with Scaling;76
5.6.1;3.6.1 V T Random Variation Trend;77
5.6.2;3.6.2 Limit of Design Solutions with Increasing 0 VT ;77
5.6.3;3.6.3 Extension of Limit of Design Solutions;79
5.6.3.1;3.6.3.1 RMW Operation with Decoupled Read Port;79
5.6.3.2;3.6.3.2 Error Correction Scheme for Redundancy;80
5.6.4;3.6.4 Area Scaling Trend Comparisons for Various Design Solutions;81
5.6.4.1;3.6.4.1 Area Comparisons of SNM and WRM Assists;83
5.6.4.2;3.6.4.2 Area Comparisons of 8T and 10T SRAMs;84
5.6.5;3.6.5 Comparisons of Design Options;85
5.7;3.7 SRAM Leakage Issues;86
5.7.1;3.7.1 SRAM Leakage Breakdown;86
5.7.2;3.7.2 SRAM Leakage Scaling Trend;87
5.7.3;3.7.3 High- Benefit for Leakage Reduction;88
5.7.4;3.7.4 Leakage Reduction;89
5.7.4.1;3.7.4.1 Power Gating Switches;89
5.7.4.2;3.7.4.2 Virtual Power Line Level Control;91
5.8;3.8 Conclusion;92
6;to 4 Ultra Low Voltage SRAM Design;95
6.1;4.1 Introduction;95
6.2;4.2 Minimum Energy and Leakage-Power Operation;96
6.3;4.3 Ultra Low Voltage SRAM Challenges;99
6.3.1;4.3.1 MOSFET Degradations at Ultra Low Voltages;101
6.3.2;4.3.2 Conventional SRAM Degradations at Ultra Low Voltages;102
6.3.2.1;4.3.2.1 Symmetric-6T Failures;102
6.3.2.2;4.3.2.2 Cell Read-Current Degradation;104
6.3.2.3;4.3.2.3 Bit-Line Leakage;105
6.4;4.4 Ultra Low Voltage Bit-Cell Design;105
6.4.1;4.4.1 Buffered-Read Bit-Cells;107
6.4.1.1;4.4.1.1 10T Bit-Cells;110
6.4.1.2;4.4.1.2 8T Bit-Cells;113
6.4.2;4.4.2 Non-buffered-Read Bit-Cells;117
6.4.2.1;4.4.2.1 7T Bit-Cell;118
6.4.2.2;4.4.2.2 Asymmetric 6T Bit-Cell;119
6.4.2.3;4.4.2.3 10T Schmitt Trigger Bit-Cell;120
6.5;4.5 Ultra Low Voltage Periphery Design;121
6.5.1;4.5.1 Column-Interleaved Layout;121
6.5.1.1;4.5.1.1 Soft-Error Correction Coding Complexity;123
6.5.1.2;4.5.1.2 Sense-Amplifier Sharing;123
6.5.2;4.5.2 Write-Assists;123
6.5.3;4.5.3 Sensing Circuits;126
6.5.3.1;4.5.3.1 Leakage Replica Scheme;126
6.5.3.2;4.5.3.2 Sense-Amplifier Redundancy;126
6.5.3.3;4.5.3.3 Small-Signal Single-Ended Sensing;128
6.6;4.6 Summary and Conclusions;129
7;to 5 Embedded DRAM in Nano-scale Technologies;133
7.1;5.1 Introduction;133
7.1.1;5.1.1 Migrating from the Commodity DRAM Base to the Logic Base;134
7.2;5.2 Fundamental DRAM Operation;136
7.2.1;5.2.1 The Capacitor;137
7.2.2;5.2.2 The Transistor;138
7.2.3;5.2.3 Cost and Process Complexity;140
7.3;5.3 Overview of Embedded DRAM Architecture;140
7.3.1;5.3.1 Single-Bank Operation;141
7.3.2;5.3.2 Multi-bank Operation;142
7.3.3;5.3.3 Macro Organization;144
7.3.4;5.3.4 Array Core Organization;145
7.3.5;5.3.5 Array Core Operation;146
7.3.6;5.3.6 Row System;146
7.3.7;5.3.7 Charge Sensing;147
7.3.8;5.3.8 Precharge Level;149
7.3.9;5.3.9 Cell Read Performance;150
7.3.10;5.3.10 Reference Cells;150
7.3.11;5.3.11 Bitline Twisting;151
7.3.12;5.3.12 Data Path;152
7.4;5.4 Test Strategy;152
7.4.1;5.4.1 BIST Engine Design Point;153
7.4.1.1;5.4.1.1 Test Multiplexor;154
7.4.1.2;5.4.1.2 Instruction Memory;154
7.4.1.3;5.4.1.3 Sequencer;155
7.4.1.4;5.4.1.4 Address Generator;155
7.4.1.5;5.4.1.5 Data Generator;155
7.4.2;5.4.2 Test and Diagnostic Capability;156
7.5;5.5 Cycle Time Advances;157
7.5.1;5.5.1 Fast Cycle Architecture;158
7.5.2;5.5.2 Compilation;160
7.5.3;5.5.3 Direct Write;161
7.5.4;5.5.4 Pipelining;163
7.5.5;5.5.5 BIST Enhancements;166
7.6;5.6 On Processor Embedded DRAM Cache;167
7.6.1;5.6.1 Current Level of Integration;167
7.6.2;5.6.2 SOI Embedded DRAM Technology Features;168
7.6.3;5.6.3 Collar Process Elimination;168
7.6.4;5.6.4 Floating Body Effects;169
7.6.5;5.6.5 Array Floating Body;170
7.6.6;5.6.6 SOI Macro Architecture;170
7.6.7;5.6.7 Pyramid Row;171
7.6.8;5.6.8 Short Bitline;172
7.6.9;5.6.9 Overhead;173
7.6.10;5.6.10 Micro Sense Amplifier (SA);173
7.6.11;5.6.11 Tertiary Sense Amplifier;174
7.6.12;5.6.12 Operation Truth Table;175
7.6.13;5.6.13 Write Waveforms;175
7.6.14;5.6.14 Read Waveforms;176
7.6.15;5.6.15 Cycle Limits;177
7.6.16;5.6.16 Micro Sense Amplifier Overhead;178
7.6.17;5.6.17 SOI Macro Features;179
7.7;5.7 Embedded DRAM Summary;179
8;to 6 Embedded Flash Memory;182
8.1;6.1 Application and Technology Trend in Embedded Nonvolatile Memories;182
8.1.1;6.1.1 Introduction;182
8.1.2;6.1.2 Market and Application Overviews for Embedded Nonvolatile Memories;185
8.1.3;6.1.3 Automotive Application Examples;189
8.1.4;6.1.4 Requirements for Embedded Flash Memory Applications and Trends;193
8.2;6.2 Embedded Flash Memory Technology;195
8.2.1;6.2.1 Floating-Gate Flash Technology;198
8.2.1.1;6.2.1.1 1Tr-NOR Cell and Operations;199
8.2.1.2;6.2.1.2 Split-Gate Cell (1.5Tr-Cell);203
8.2.1.3;6.2.1.3 2Tr Cell for Low-Voltage, Low-Power Operations;208
8.2.2;6.2.2 Charge-Trapping Flash Technologies, SONOS and Nano-dot;209
8.2.2.1;6.2.2.1 SONOS Basics;210
8.2.2.2;6.2.2.2 Recent SONOS Trends;211
8.2.2.3;6.2.2.3 SONOS Cell with Localized Charge Trapping;212
8.2.2.4;6.2.2.4 Split-Gate SONOS Cell;216
8.2.2.5;6.2.2.5 2Tr SONOS Cell;219
8.2.2.6;6.2.2.6 Nano-dot Memory Device;220
8.2.2.7;6.2.2.7 Advantages and Challenges in Charge-Trapping Flash Devices;221
8.3;6.3 Embedded Flash Memory Design;1
8.3.1;6.3.1 Benefits of Embedded Flash Memory and Design Considerations;222
8.3.2;6.3.2 Basic Flash Memory Design with Floating-Gate 1Tr-NOR Cell;225
8.3.3;6.3.3 Embedded Flash Memory Design Examples;230
8.3.3.1;6.3.3.1 High-Performance Flash-MCU Design;231
8.3.3.2;6.3.3.2 Embedded Flash Memory Design for Reconfigurable Logic;234
8.3.3.3;6.3.3.3 Fully CMOS-Compatible Nonvolatile Storage Design by CMOS Flash;235
8.3.3.4;6.3.3.4 Fully CMOS-Compatible Nonvolatile Storage Design by OTP (Fuse);239
8.3.4;6.3.4 Future Trend in Embedded Flash Memory Technology and Design;241
9;to 7 Embedded Magnetic RAM;246
9.1;7.1 Embedded Magnetic RAM Technology and Design;246
9.1.1;7.1.1 MRAM Basics;246
9.1.1.1;7.1.1.1 History of MRAM;246
9.1.1.2;7.1.1.2 Principle of TMR-MRAM;252
9.1.2;7.1.2 MRAM Integration and Basic Design;255
9.1.2.1;7.1.2.1 MRAM Cell Structure and Integration;255
9.1.2.2;7.1.2.2 Basic TMR-MRAM Design Considerations;257
9.1.2.3;7.1.2.3 Basic TMR-MRAM Design;259
9.1.2.4;7.1.2.4 MRAM Cell Architectures;264
9.1.2.5;7.1.2.5 Spin-Torque Switching MRAM;266
9.2;7.2 MRAM Design Examples and Applications;268
9.2.1;7.2.1 MRAM Design Examples;268
9.2.1.1;7.2.1.1 A 4 Mbit MRAM with Toggle Mode of Operation;268
9.2.1.2;7.2.1.2 A 16 Mbit MRAM with Dummy Column Architecture;271
9.2.1.3;7.2.1.3 A 1Tr-4MTJ MRAM with Self-Reference Sensing '13322'135;272
9.2.1.4;7.2.1.4 A New Field-Switching Scheme with A 2T-1MTJ Cell '133 18 , 19 '135;272
9.2.2;7.2.2 MRAM Applications and Future Challenges;274
9.3;7.3 Embedded Nonvolatile Memory Frontiers and Challenges;276
9.4;7.4 Conclusions;280
10;to 8 FeRAM;283
10.1;8.1 Introduction;283
10.2;8.2 Ferroelectric Materials;283
10.2.1;8.2.1 Fundamentals of Ferroelectric Materials;284
10.2.2;8.2.2 Electrical Characteristics;289
10.3;8.3 FeRAM Cells and Circuit Technology;298
10.3.1;8.3.1 FeRAM Cell Physical and Schematic Structures;298
10.3.2;8.3.2 Basic Sensing Architectures;303
10.3.3;8.3.3 Redundancy and Data Protection for FeRAM;310
10.3.4;8.3.4 Circuit Challenges to Fatigue-Free Operation or Nondestructive Read Out;313
10.4;8.4 Current FeRAM Markets;316
10.5;8.5 Low-Voltage Challenges and Future Trends;321
10.5.1;8.5.1 Low-Voltage Challenges;322
10.5.2;8.5.2 Future Trends;324
11;to 9 Statistical Blockade: Estimating Rare Event Statistics for Memories;333
11.1;9.1 Introduction;333
11.2;9.2 The Parametric Yield of Memory Arrays;334
11.2.1;9.2.1 Simple, Approximate Analysis;335
11.2.2;9.2.2 Accurate Analysis;335
11.2.3;9.2.3 Incorporating Redundancy;336
11.2.4;9.2.4 The Poisson Yield Model;338
11.2.4.1;9.2.4.1 An Example: Quantifying Fault Tolerance with Statistical Analysis;339
11.3;9.3 Estimating Failure Statistics with Monte Carlo Simulation;340
11.3.1;9.3.1 Process Variation Statistics: Prerequisites for Statistical Analysis;340
11.3.2;9.3.2 Monte Carlo Simulation;341
11.3.3;9.3.3 The Problem with Memories;342
11.3.4;9.3.4 Methods for Estimating Rare Events Statistics;342
11.3.5;9.3.5 Methods in this Chapter: A Brief Overview;343
11.4;9.4 Modeling Rare Event Statistics;344
11.4.1;9.4.1 The Tail Modeling Problem;345
11.4.2;9.4.2 Extreme Value Theory: Tail Distributions;346
11.4.3;9.4.3 Estimating the Tail: Fitting the GPD to Data;349
11.4.3.1;9.4.3.1 Maximum Likelihood Estimation;350
11.4.3.2;9.4.3.2 Moment Matching;351
11.4.3.3;9.4.3.3 Probability-Weighted Moment Matching;352
11.5;9.5 Statistical Blockade;353
11.5.1;9.5.1 Classification;353
11.5.1.1;9.5.1.1 Support Vector Classifier;354
11.5.2;9.5.2 The Statistical Blockade Algorithm;358
11.5.2.1;9.5.2.1 Note on Choosing and Unbiasing the Classifier;360
11.5.3;9.5.3 Experimental Results;361
11.5.3.1;9.5.3.1 6T SRAM Cell;363
11.5.3.2;9.5.3.2 64-bit SRAM Column;365
11.5.3.3;9.5.3.3 Master--Slave Flip-Flop with Scan Chain;368
11.6;9.6 Making Statistical Blockade Practical;371
11.6.1;9.6.1 Conditionals and Disjoint Tail Regions;372
11.6.1.1;9.6.1.1 The Problem;372
11.6.1.2;9.6.1.2 The Solution;374
11.6.2;9.6.2 Extremely Rare Events and Their Statistics;375
11.6.2.1;9.6.2.1 Extremely Rare Events;375
11.6.2.2;9.6.2.2 The Reason for Error in the MSFF Tail Model;377
11.6.2.3;9.6.2.3 The Problem;378
11.6.3;9.6.3 A Recursive Formulation of Statistical Blockade;379
11.6.4;9.6.4 Experimental Results;382
12;Index;387