Bauer / Henkel Run-time Adaptation for Reconfigurable Embedded Processors

1. Auflage 2010
ISBN: 978-1-4419-7412-9
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 223 Seiten

Embedded processors are the heart of embedded systems. Reconfigurable embedded processors comprise an extended instruction set that is implemented using a reconfigurable fabric (similar to a field-programmable gate array, FPGA). This book presents novel concepts, strategies, and implementations to increase the run-time adaptivity of reconfigurable embedded processors. Concepts and techniques are presented in an accessible, yet rigorous context. A complex, realistic H.264 video encoder application with a high demand for adaptivity is presented and used as an example for motivation throughout the book. A novel, run-time system is demonstrated to exploit the potential for adaptivity and particular approaches/algorithms are presented to implement it.

Autoren/Hrsg.

Bauer, Lars

Henkel, Jörg

Inhaltsverzeichnis

1;Run-time Adaptation for Reconfigurable Embedded Processors;3
1.1;Contents;5
1.2;Abbreviations;9
1.3;List of Figures;13
1.4;List of Tables;19
1.5;List of Algorithms;21
1.6;Chapter 1: Introduction;22
1.6.1;1.1 Application-Specific Instruction Set Processors;23
1.6.2;1.2 Reconfigurable Processors;24
1.6.2.1;1.2.1 Summary of Reconfigurable Processors;25
1.6.3;1.3 Contribution of this Monograph;26
1.6.4;1.4 Monograph Outline;27
1.7;Chapter 2: Background and Related Work;29
1.7.1;2.1 Extensible Processors;29
1.7.2;2.2 Reconfigurable Processors;31
1.7.2.1;2.2.1 Granularity of the Reconfigurable Fabric;31
1.7.2.2;2.2.2 Using and Partitioning the Reconfigurable Area;37
1.7.2.3;2.2.3 Coupling Accelerators and the Processor;41
1.7.2.4;2.2.4 Reconfigurable Instruction Set Processors;43
1.7.3;2.3 Summary of Related Work;46
1.8;Chapter 3: Modular Special Instructions;48
1.8.1;3.1 Problems of State-of-the-Art Monolithic Special Instructions;48
1.8.2;3.2 Hierarchical Special Instruction Composition;53
1.8.3;3.3 Example Special Instructions for the ITU-T H.264 Video Encoder Application;60
1.8.4;3.4 Formal Representation and Combination of Modular Special Instructions;68
1.8.5;3.5 Summary of Modular Special Instructions;72
1.9;Chapter 4: The RISPP Run-Time System;74
1.9.1;4.1 RISPP Architecture Overview;74
1.9.1.1;4.1.1 Summary of the RISPP Architecture Overview;77
1.9.2;4.2 Requirement Analysis and Overview;77
1.9.2.1;4.2.1 Summary of the Requirement Analysis and Overview;84
1.9.3;4.3 Online Monitoring and Special Instruction Forecasting;85
1.9.3.1;4.3.1 Fine-Tuning the Forecast Values;88
1.9.3.2;4.3.2 Evaluation of Forecast Fine-Tuning;92
1.9.3.3;4.3.3 Hardware Implementation for Fine-Tuning the Forecast Values;95
1.9.4;4.3.4 Summary of the Online Monitoring and SI Forecasting;98
1.9.5;4.4 Molecule Selection;99
1.9.5.1;4.4.1 Problem Description for Molecule Selection;100
1.9.5.2;4.4.2 Parameter Identification for the Profit Function;103
1.9.5.3;4.4.3 Heuristic Solution for the Molecule Selection;106
1.9.5.4;4.4.4 Evaluation and Results for the Molecule Selection;109
1.9.5.5;4.4.5 Summary of the Molecule Selection;115
1.9.6;4.5 Reconfiguration-Sequence Scheduling;116
1.9.6.1;4.5.1 Problem Description for Reconfiguration-Sequence Scheduling;117
1.9.6.2;4.5.2 Determining the Molecule Reconfiguration Sequence;120
1.9.6.3;4.5.3 Evaluation and Results for the Reconfiguration-Sequence Scheduling;125
1.9.7;4.5.4 Summary of the Reconfiguration-Sequence Scheduling;128
1.9.8;4.6 Atom Replacement;129
1.9.8.1;4.6.1 Motivation and Problem Description of State-of-the-Art Replacement Policies;129
1.9.8.2;4.6.2 The MinDeg Replacement Policy;133
1.9.8.3;4.6.3 Evaluation and Results;136
1.9.9;4.6.4 Summary of the Atom Replacement;141
1.9.10;4.7 Summary of the RISPP Run-Time System;142
1.10;Chapter 5: RISPP Architecture Details;144
1.10.1;5.1 Special Instructions as Interface Between Hardware and Software;145
1.10.2;5.2 Executing Special Instructions Using the Core Instruction Set Architecture;150
1.10.3;5.3 Data Memory Access for Special Instructions;155
1.10.4;5.4 Atom Infrastructure;158
1.10.4.1;5.4.1 Atom Containers and Bus Connectors;162
1.10.4.2;5.4.2 Load/Store- and Address Generation Units;167
1.10.4.3;5.4.3 Summary of the Atom Infrastructure;171
1.10.5;5.5 RISPP Prototype Implementation and Results;171
1.10.6;5.6 Summary of the RISPP Architecture Details;182
1.11;Chapter 6: Benchmarks and Comparisons;183
1.11.1;6.1 Benchmarking the RISPP Approach for Different Architectural Parameters;184
1.11.2;6.2 Comparing Different Architectures;187
1.11.2.1;6.2.1 Assumptions and Similarities;188
1.11.2.2;6.2.2 Dissimilarities;189
1.11.2.3;6.2.3 Fairness of Comparison;190
1.11.2.4;6.2.4 Summary of Comparing Different Architectures;191
1.11.3;6.3 Comparing RISPP with Application-Specific Instruction Set Processors;192
1.11.4;6.4 Comparing RISPP with Reconfigurable Processors;200
1.11.5;6.5 Summary of Benchmarks and Comparisons;205
1.12;Chapter 7: Conclusion and Outlook;208
1.12.1;7.1 Summary;208
1.12.2;7.2 Future Work;210
1.13;Appendix A: RISPP Simulation;213
1.14;Appendix B: RISPP Prototype;220
1.15;Bibliography;225
1.16;Index;234