Ho-Ming / Tong / Lai Advanced Flip Chip Packaging

1. Auflage 2013
ISBN: 978-1-4419-5768-9
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 560 Seiten

Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable.

Autoren/Hrsg.

Tong, Ho-Ming

Lai, Yi-Shao

Wong, C.P.

Wong, C. P.

Inhaltsverzeichnis

1;Preface;6
2;Contents;8
3;Chapter 1: Market Trends: Past, Present, and Future;9
3.1;1.1 Flip Chip Technology Overview and Early Beginnings;9
3.2;1.2 Wafer Bumping Technology Overview;10
3.3;1.3 Evaporation (C4);11
3.3.1;1.3.1 Stencil Printing;11
3.3.2;1.3.2 Electroplating;13
3.3.3;1.3.3 Solder Dam;13
3.3.4;1.3.4 Plating Outside a Defined Structure;15
3.4;1.4 Wafer Bump Summary;17
3.4.1;1.4.1 Substrate Technology;17
3.5;1.5 Flip Chip Industry and Infrastructure Development;18
3.6;1.6 Flip Chip Market Trends Covering C4;22
3.7;1.7 Flip Chip Market Drivers Including the Need for More Package Co-design and IC-Package-System Co-design Involving Cu/Low K ...;24
3.8;1.8 Migration of Flip Chip from IDM´s to SAT´s Providers;26
3.9;1.9 Implications of the Advent of Tighter Environmental Regulations Covering Underfill, Solder, Structural Design, etc.;28
3.10;1.10 Mounting Cost Pressures and Implications for Flip Chip, etc.;28
3.11;References;29
4;Chapter 2: Technology Trends: Past, Present, and Future;30
4.1;2.1 Evolution of Flip Chip Technologies in Response to IC and System Technology Trends;30
4.2;2.2 Evolution of First Level Packaging;34
4.2.1;2.2.1 Thermal Demands;34
4.2.2;2.2.2 Increased Chip Size;34
4.2.3;2.2.3 Restriction of Hazardous Substances;36
4.2.4;2.2.4 Compliance Cost, and Future RoHS Directive;37
4.2.5;2.2.5 Choice of Sn;38
4.2.6;2.2.6 Solder Void;40
4.2.7;2.2.7 Soft Error and Alpha Emission;40
4.3;2.3 First Level Packaging Challenges;41
4.3.1;2.3.1 Weaker BEOL Structures;41
4.3.2;2.3.2 C4 Electromigration;42
4.3.3;2.3.3 Cu Pillar Technology;44
4.4;2.4 IC Technology Roadmaps: More Moore and More Than Moore;45
4.4.1;2.4.1 Improvements in Laminate Ground Rules;48
4.5;2.5 3D Flip Chip SiPs for Handhelds Require IC-Package-System Co-design;48
4.5.1;2.5.1 SIP Engineering Challenges and Co-design Tool;49
4.6;2.6 PoP and Stacked Packages;51
4.6.1;2.6.1 Embedded Chip Packages;52
4.6.2;2.6.2 Folded Stacked Packages;53
4.7;2.7 Emerging Flip Chip Technologies;54
4.8;2.8 Summary;57
4.9;References;57
5;Chapter 3: Bumping Technologies;60
5.1;3.1 Introduction;60
5.2;3.2 Materials and Processes for Bumping Technology;61
5.2.1;3.2.1 Metals for Wafer Bumping;61
5.2.1.1;3.2.1.1 Under Bump Metallization;62
5.2.1.2;3.2.1.2 Bumping Technologies;63
5.2.1.3;3.2.1.3 Bump Metallurgy;73
5.2.1.3.1;Bumps Based on Gold and AuSn;73
5.2.1.3.2;Bumps Based on Solder;75
5.2.1.3.3;Copper Posts (Pillars);76
5.2.1.3.4;Plating of Ni;78
5.2.1.4;3.2.1.4 Plating of Alloys;78
5.3;3.3 Recent Advances on Bumping Technologies;83
5.3.1;3.3.1 Low Cost Solder Bumping Process: Solder Bump Maker;83
5.3.2;3.3.2 Nanoporous Interconnect;83
5.3.3;3.3.3 Inclined Microbump;83
5.3.4;3.3.4 Fine Pitch Imprinting Bumping;85
5.3.5;3.3.5 Solder Bumping by Liquid Droplet Microgripper;86
5.3.6;3.3.6 CNT Bumps;88
5.4;References;90
6;Chapter 4: Flip-Chip Interconnections: Past, Present, and Future;92
6.1;4.1 Evolution of Flip-Chip Interconnection Technologies;93
6.1.1;4.1.1 High-Pb-Based Solder Joint;94
6.1.2;4.1.2 High-Pb Solder on Chip Joined to Eutectic Solder on Laminate Carrier;94
6.1.3;4.1.3 Pb-Free Solder Joint;96
6.1.4;4.1.4 Cu Pillar Joint;96
6.2;4.2 Evolution of Enabling Assembly Technologies;98
6.2.1;4.2.1 Wafer Thinning and Wafer Dicing (Covering Cu/low k Devices);98
6.2.2;4.2.2 Wafer Bumping;99
6.2.3;4.2.3 Flux and Flux Cleaning;102
6.2.4;4.2.4 Reflow Soldering, Thermo-compression Bonding;103
6.2.5;4.2.5 Underfill and Over-Mold;105
6.2.6;4.2.6 Quality Assurance Methodologies;107
6.3;4.3 C4NP Technology;108
6.3.1;4.3.1 C4NP Wafer Bumping Processes;109
6.3.2;4.3.2 Mold Fabrication and Solder Transfer to Wafer;109
6.3.3;4.3.3 Wafer Bumping Yield Improvements;110
6.3.4;4.3.4 C4NP Advantages: Alloy Flexibility;113
6.4;4.4 Fabrication of Cu Pillar Bumps;115
6.5;4.5 Substrate Bumping Technologies;115
6.6;4.6 Pb-Free Solders for Flip-Chip Applications;122
6.6.1;4.6.1 Properties of Pb-Free Solders;123
6.6.2;4.6.2 Solidification, Microstructure, and Undercooling;125
6.7;4.7 Interfacial Reactions in Pb-Free, Flip-Chip Joints;126
6.7.1;4.7.1 Ball-Limiting Metallurgy or Under Bump Metallization;126
6.7.2;4.7.2 Substrate Metallization;128
6.7.3;4.7.3 Interfacial Reactions in Pb-Free Solder Joints;129
6.8;4.8 Reliability of Flip-Chip Interconnect Structure;133
6.8.1;4.8.1 Thermal Fatigue;133
6.8.2;4.8.2 Drop Impact Reliability;134
6.8.3;4.8.3 Chip-Package-Interaction: Interlayer Dielectric Cracking During Module Assembly;136
6.8.4;4.8.4 Electromigration Reliability;140
6.8.5;4.8.5 Sn Pest;148
6.9;4.9 Future Trends in Flip-Chip Technology;148
6.9.1;4.9.1 Conventional Micro-Solder Joint;149
6.9.2;4.9.2 Metal-to-Metal Solid-State Diffusion Bonding;151
6.10;4.10 Concluding Remark;153
6.11;References;154
7;Chapter 5: Flip Chip Underfill: Materials, Process, and Reliability;162
7.1;5.1 Introduction;162
7.2;5.2 Conventional Underfill Materials and Process;165
7.3;5.3 Characterizations of Underfill Materials;167
7.3.1;5.3.1 Differential Scanning Calorimeter Measured Curing Kinetics;167
7.3.2;5.3.2 DSC Measured Tg;170
7.3.3;5.3.3 TMA Measured Coefficient of Thermal Expansion;171
7.3.4;5.3.4 DMA Measured Dynamic Moduli;172
7.3.5;5.3.5 TGA Measured Thermal Stability;173
7.3.6;5.3.6 Flexure Test;174
7.3.7;5.3.7 Viscosity Measurement;175
7.3.8;5.3.8 Adhesion of the Underfill to Die Passivation;175
7.3.9;5.3.9 Moisture Absorption;176
7.4;5.4 Reliability of Flip Chip Underfill Packages;176
7.4.1;5.4.1 Effect of Passivation Layer;179
7.4.2;5.4.2 Adhesion Degradation Versus 85/85 Aging Time;180
7.4.3;5.4.3 Improvement of Adhesion Hydrolytic Stability Through Coupling Agents;183
7.5;5.5 New Challenges to Underfill;185
7.6;5.6 No-Flow Underfill;188
7.6.1;5.6.1 Approaches of Incorporating Silica Fillers into No-Flow Underfill;192
7.7;5.7 Molded Underfill;195
7.8;5.8 Wafer Level Underfill;197
7.9;5.9 Summary;201
7.10;References;202
8;Chapter 6: Conductive Adhesives for Flip-Chip Applications;207
8.1;6.1 Introduction;207
8.2;6.2 Anisotropically Conductive Adhesives/Films;208
8.2.1;6.2.1 Overview of ACAs/ACFs;208
8.2.2;6.2.2 Categories;208
8.2.3;6.2.3 Adhesive Matrix;209
8.2.4;6.2.4 Conductive Fillers;210
8.2.4.1;6.2.4.1 Solid Metal Particles;210
8.2.4.2;6.2.4.2 Non-metal Particles with Metal Coating;210
8.2.4.3;6.2.4.3 Metal Particles with Insulating Coating;210
8.2.5;6.2.5 Flip-Chip Applications Using ACAs/ACFs;210
8.2.5.1;6.2.5.1 ACA Flip Chip for Bumped Dies;211
8.2.5.1.1;Two Filler Systems;211
8.2.5.1.2;Coated Plastic Filler;212
8.2.5.1.3;Solder Filler Systems;212
8.2.5.1.4;Ni Filler;213
8.2.5.2;6.2.5.2 ACA Bumped Flip Chips on Glass Chip Carriers;214
8.2.5.2.1;Selective Tacky Adhesive Method;214
8.2.5.2.2;The MAPLE Method;215
8.2.5.3;6.2.5.3 ACA Bumped Flip Chips for High Frequency Applications;216
8.2.5.4;6.2.5.4 ACA for Unbumped Flip Chips;216
8.2.5.4.1;Gold-Coated Nickel Filler;217
8.2.5.4.2;Ni/Au Coated Silver Filler;217
8.2.5.4.3;Conductive Columns;217
8.2.6;6.2.6 Failure Mechanism of ACA/ACF Interconnections;218
8.2.6.1;6.2.6.1 Oxidation of Non-noble Metals;219
8.2.6.2;6.2.6.2 Loss of Compressive Force;219
8.2.7;6.2.7 Recent Advances in Nano-ACAs/ACFs;219
8.2.7.1;6.2.7.1 Low Temperature Sintering of Nano-Ag-Filled ACAs/ACFs;219
8.2.7.2;6.2.7.2 Self-Assembled Monolayers for Nano-ACAs/ACFs;220
8.2.7.3;6.2.7.3 Silver Migration Control in Nano-Silver Filled ACAs;222
8.2.7.4;6.2.7.4 ACF with Straight-Chain-Like Nickel Nanoparticles;224
8.2.7.5;6.2.7.5 Nanowire ACFs for Ultrafine Pitch Flip-Chip Interconnection;224
8.2.7.6;6.2.7.6 In-Situ Formation of Nano-Conductive Fillers in ACAs/ACFs;226
8.3;6.3 Isotropically Conductive Adhesives;226
8.3.1;6.3.1 Introduction;226
8.3.1.1;6.3.1.1 Percolation Theory of Conduction;226
8.3.1.2;6.3.1.2 Adhesive Matrix;227
8.3.1.3;6.3.1.3 Conductive Fillers;229
8.3.1.3.1;Pure Silver vs. Ag-Coated Fillers;230
8.3.1.3.2;Particle Shape and Size;230
8.3.1.3.3;Nano-Sized Fillers;230
8.3.1.3.4;Silver-Copper Fillers;231
8.3.1.3.5;Cu Fillers;231
8.3.1.3.6;Low-Melt Fillers;233
8.3.2;6.3.2 Flip-Chip Applications Using ICAs;234
8.3.2.1;6.3.2.1 ICA Process for Unbumped Chips;234
8.3.2.1.1;Flip Chip with Printed ICA Bumps;234
8.3.2.1.1.1;UBM Deposition;235
8.3.2.1.1.2;ICA Printing;235
8.3.2.1.1.3;ICA Bump Curing;236
8.3.2.1.1.4;Underfilling;236
8.3.2.1.2;Flip Chip with Micromachined ICA Bumps;236
8.3.2.2;6.3.2.2 Metal-Bumped Flip-Chip Joints;239
8.3.2.3;6.3.2.3 Carbon Nanotube Flip Chip;240
8.3.3;6.3.3 ICAs for Advanced Packaging Applications;242
8.3.3.1;6.3.3.1 Solar Cell;242
8.3.3.2;6.3.3.2 3D Stacking;244
8.3.3.3;6.3.3.3 Microspring;244
8.3.4;6.3.4 High Frequency Performance of ICA Joints;247
8.3.5;6.3.5 Reliability of ICA Joints;247
8.3.6;6.3.6 Recent Advances on Nano-ICAs;250
8.3.6.1;6.3.6.1 ICAs with Silver Nanowires;250
8.3.6.2;6.3.6.2 Effect of Nano-Sized Silver Particles on the Conductivity of ICAs;251
8.3.6.3;6.3.6.3 ICAs Filled with Aggregates of Nano-sized Ag Particles;252
8.3.6.4;6.3.6.4 ICAs Filled with Nano-sized Ni Particles;252
8.3.6.5;6.3.6.5 Nano-ICAs Filled with CNT;253
8.3.6.5.1;Electrical and Mechanical Characterization of CNT-Filled ICAs;253
8.3.6.5.2;Effect of Adding CNTs to the Electrical Properties of ICAs;254
8.3.6.5.3;Composites Filled with Surface Treated CNT;255
8.4;6.4 Nonconductive Adhesive for Flip-Chip Applications;255
8.4.1;6.4.1 Recent Developments on NCA Flip Chip;257
8.4.1.1;6.4.1.1 NCAs with Low CTE;257
8.4.1.2;6.4.1.2 Fine Pitch Chip-on-Flex by Pre-applied Wafer Level Adhesives;258
8.4.1.3;6.4.1.3 Fast Curing NCA;259
8.4.1.4;6.4.1.4 NCAs Versus ACAs in Flex Circuits;259
8.5;References;259
9;Chapter 7: Substrate Technology;268
9.1;7.1 Introduction;268
9.2;7.2 Type of Construction;269
9.2.1;7.2.1 Sequential Build-Up Structure;270
9.2.2;7.2.2 Z-Stack Structure;271
9.3;7.3 Sequential Build-Up Substrate;271
9.3.1;7.3.1 Process Flow;272
9.3.2;7.3.2 Conductor Line;273
9.3.3;7.3.3 Micro-Via Hole;283
9.3.4;7.3.4 Pad Finish;292
9.3.5;7.3.5 Chip Package Interaction;301
9.3.6;7.3.6 Reliability;310
9.3.7;7.3.7 Historical Milestone;317
9.4;7.4 Z-Stack Type Substrate;319
9.4.1;7.4.1 Z-Stack Substrate With Pattern Transfer;319
9.4.2;7.4.2 Any Layer Via Substrate;324
9.4.3;7.4.3 Embedded Component Substrate;324
9.4.4;7.4.4 Substrate With PTFE Material;328
9.5;7.5 Challenges;329
9.5.1;7.5.1 Coreless Structure;329
9.5.2;7.5.2 Trench Structure;332
9.5.3;7.5.3 Ultralow CTE;333
9.5.4;7.5.4 Substrate for Stacked Chip;334
9.5.5;7.5.5 Optical Wave Guide;337
9.6;7.6 Ceramic Substrate;338
9.7;7.7 Roadmap;338
9.7.1;7.7.1 JEITA;338
9.7.2;7.7.2 ITRS;342
9.8;7.8 Summary;343
9.9;References;343
10;Chapter 8: IC-Package-System Integration Design;345
10.1;8.1 Integrated Chip-Package-System: What, How, and Why?;347
10.1.1;8.1.1 Introduction;347
10.1.1.1;8.1.1.1 Overview;347
10.1.2;8.1.2 Design Explorations;349
10.1.2.1;8.1.2.1 On-Chip Design Decisions;351
10.1.2.1.1;I/O Circuit Design;351
10.1.2.1.2;I/O Buffer Physical Planning;352
10.1.2.1.3;On-Chip Power Design and Planning;353
10.1.2.2;8.1.2.2 Package Design and Exploration;353
10.1.2.2.1;Package Stack-Up Order;354
10.1.2.2.2;Substrate Layer Assignment;354
10.1.2.2.3;Voltage Domain Planning;354
10.1.3;8.1.3 Modeling and Analysis Decisions;356
10.1.4;8.1.4 ICPS Design Problems;356
10.1.4.1;8.1.4.1 Design and Planning of Power Delivery System;357
10.1.4.2;8.1.4.2 Design and Planning of Signal Interface;357
10.1.4.2.1;Signal Interface Characterization;357
10.2;8.2 Decoupling Capacitor Insertion;359
10.2.1;8.2.1 Introduction;359
10.2.2;8.2.2 Electrical Models;361
10.2.2.1;8.2.2.1 Package Model;361
10.2.2.2;8.2.2.2 Decoupling Capacitor Model;362
10.2.2.3;8.2.2.3 Model of I/O Cells;362
10.2.3;8.2.3 Impedance Metric and Its Incremental Computation;364
10.2.4;8.2.4 Noise Metric;366
10.2.5;8.2.5 Simulated-Annealing-Based Decap Insertion;367
10.2.5.1;8.2.5.1 Settings;367
10.2.5.2;8.2.5.2 Algorithm;368
10.2.5.3;8.2.5.3 Results;369
10.2.5.3.1;Case 1;369
10.2.5.3.2;Case 2;370
10.2.5.4;8.2.5.4 Runtime;371
10.2.6;8.2.6 Sensitivity-Based Decap Insertion;372
10.2.6.1;8.2.6.1 Improved Model and Problem Formulation;372
10.2.6.2;8.2.6.2 Parameterized Circuit Equation;374
10.2.6.3;8.2.6.3 I/O Current Correlation and Spectral Clustering;376
10.2.6.4;8.2.6.4 Localized Integrity Analysis;378
10.2.6.4.1;Network Decomposition;378
10.2.6.4.2;Triangular Block-Structured Reduction;379
10.2.6.5;8.2.6.5 Algorithm and Experimental Results;381
10.2.6.5.1;Sensitivity-Based Optimization;381
10.2.6.5.2;Experimental Results;382
10.3;8.3 TSV-Based 3D Stacking: The Good, the Bad, and the Powerful;385
10.3.1;8.3.1 Introduction About 3D IC Stacking Techniques;385
10.3.2;8.3.2 Challenges;388
10.3.2.1;8.3.2.1 Thermal and Power Distribution Issues of 3D IC;388
10.3.2.2;8.3.2.2 Testing Issues of 3D IC;390
10.3.3;8.3.3 Solutions;393
10.3.3.1;8.3.3.1 3D IC Design Automation Considering Dynamic Power and Thermal Integrity;393
10.3.3.1.1;TSV Allocation Problem;394
10.3.3.1.2;Algorithm;395
10.3.3.1.2.1;Complexity Compression of States;395
10.3.3.1.2.2;Complexity Compression of I/Os;396
10.3.3.1.2.3;Dynamic Integrity and Sensitivity by Structured and Parameterized Macromodel;398
10.3.3.1.3;Results;400
10.3.3.1.3.1;Experimental Setup;400
10.3.3.1.3.2;Results Analysis;400
10.3.3.2;8.3.3.2 Fault-Tolerant 3D Clock Scheme;402
10.3.3.2.1;Clock Design with TFU;402
10.3.3.2.2;Algorithm;404
10.3.3.2.2.1;TSV Fault-Tolerant Unit;404
10.3.3.2.2.2;TSV Pairing and Buffer Insertion;404
10.3.3.2.2.3;TFU Integration with Clock Tree Synthesis;405
10.3.3.2.3;Results;407
10.3.3.2.3.1;Experimental Setup;407
10.3.3.2.3.2;Results Analysis;408
10.4;8.4 Summary;410
10.5;References;411
11;Chapter 9: Thermal Management of Flip Chip Packages;417
11.1;9.1 Introduction;418
11.2;9.2 Heat Transfer Fundamentals;419
11.3;9.3 Electro-thermal Analog Model;422
11.4;9.4 Thermal Management Objectives;424
11.5;9.5 Thermal Management at the Die and Package Level;425
11.6;9.6 Hot Spots in Chip Dies;427
11.7;9.7 Analytical Modeling of Chip Hot Spots;428
11.8;9.8 Chip Thinning;434
11.9;9.9 Thermal Interface Materials;434
11.10;9.10 System Level Thermal Management;436
11.11;9.11 Conduction Heat Spreaders;438
11.12;9.12 Heat Pipes;438
11.13;9.13 Air-Cooled Heat Sinks;441
11.14;9.14 Liquid Cooled Cold Plates;442
11.15;9.15 Internal Hybrid Liquid-Air Cooling Systems;444
11.16;9.16 Refrigeration Cooled Systems;446
11.17;9.17 Emerging Research Areas and Technologies;451
11.18;9.18 Direct Immersion Cooling;451
11.19;9.19 3D Chip Stacks;455
11.20;9.20 Advanced Thermal Interfaces;457
11.21;9.21 Synthetic Jets and Actuated Flow Devices;458
11.22;9.22 Multi-Core Focused Chip Cooling;459
11.23;9.23 Thermoelectric Enhanced Cooling;459
11.24;9.24 Measurements and Modeling;462
11.25;9.25 Package Thermal Measurements;462
11.26;9.26 Temperature Measurement Device and Method;464
11.27;9.27 Temperature Measurement Standards;464
11.28;9.28 Compact Thermal Models;465
11.29;9.29 FEM/CFD Modeling;467
11.30;References;469
12;Chapter 10: Thermo-mechanical Reliability in Flip-Chip Packages;474
12.1;10.1 Overview of Thermo-mechanical Reliability Issues in Flip-Chip Packages;475
12.2;10.2 Thermal Deformation in Flip-Chip Assembly;477
12.2.1;10.2.1 Consistent Composite Plate Model;477
12.2.2;10.2.2 Free Thermal Deformation;479
12.2.3;10.2.3 Die Stress Estimation with Bi-material Plate Model;481
12.2.4;10.2.4 Minimizing Chip-Packaging Interaction;483
12.2.5;10.2.5 Summary of Thermal Deformation in Flip-Chip Assembly;487
12.3;10.3 Solder Bump Reliability in Flip-Chip Assembly;487
12.3.1;10.3.1 Thermal Strain Measurement in Solder Bumps;488
12.3.2;10.3.2 Constitutive Equation for Solder;491
12.3.3;10.3.3 Reliability Modeling for Solder Joint;496
12.3.4;10.3.4 Underfill Adhesion Strength on Solder Bump Reliability;500
12.3.5;10.3.5 Summary of Solder Bump Reliability;502
12.4;References;503
13;Chapter 11: Interfacial Reactions and Electromigration in Flip-Chip Solder Joints;505
13.1;11.1 Introduction;506
13.2;11.2 Interfacial Reactions of Lead-Free Solders with Substrates;507
13.2.1;11.2.1 Dissolution and Its Kinetics During Reflow;508
13.2.2;11.2.2 Reaction of Lead-Free Solders with Cu-Based Pads;512
13.2.3;11.2.3 Reaction of Lead-Free Solders with Ni-Based Pads;512
13.2.3.1;11.2.3.1 Uncomplicated Cu Concentration Effect;513
13.2.4;11.2.4 Cross-interaction Between Cu and Ni Across a Solder Joint;518
13.2.4.1;11.2.4.1 Cross-interaction During Reaction with Molten Solders (Reflow);519
13.2.4.2;11.2.4.2 Cross-interaction During Reaction with Solid Solders (Aging);521
13.2.5;11.2.5 Effect of Alloying with Other Active Elements;521
13.2.5.1;11.2.5.1 Fe, Co, and Ni Additions;522
13.2.5.2;11.2.5.2 Zn Addition;523
13.2.5.3;11.2.5.3 Cu Addition;525
13.2.6;11.2.6 Effect of Small Solder Volume;525
13.2.6.1;11.2.6.1 Exhaustion of the Active Element Due to Smaller Solder Volume;526
13.2.6.2;11.2.6.2 Excessive Intermetallic Formation Due to Small Solder Volume;529
13.3;11.3 Electromigration in Flip-Chip Solder Joints;530
13.3.1;11.3.1 Fundamentals of Electromigration;531
13.3.2;11.3.2 Effect of Current Stressing on Solder and the Resulting Failure Mechanism;534
13.3.2.1;11.3.2.1 Low Critical Product of Solder Alloys;535
13.3.2.2;11.3.2.2 Current Crowding in Flip-Chip Solder Joints;536
13.3.2.3;11.3.2.3 Pancake-Type Void Formation Within Solder on the Cathode Side;536
13.3.2.4;11.3.2.4 Comparison Between Eutectic Sn-Pb and Sn-Ag-Cu Solders Under Current Stressing;541
13.3.3;11.3.3 Effect of Current Stressing on UBM and the Resulting Failure Mechanism;541
13.3.3.1;11.3.3.1 Dissolution of Cu UBM;542
13.3.3.2;11.3.3.2 Dissolution of Ni UBM;544
13.3.3.3;11.3.3.3 Temperature Effect on the UBM Dissolution;548
13.3.4;11.3.4 Mean-Time-to Failure of Flip-Chip Solder Joints;551
13.3.5;11.3.5 Mitigation Strategy Against Electromigration;552
13.4;11.4 Emerging Issues;554
13.5;References;555