Horiguchi / Itoh Nanoscale Memory Repair

1. Auflage 2011
ISBN: 978-1-4419-7958-2
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 218 Seiten

Reihe: Integrated Circuits and Systems

Yield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. This book systematically describes these yield and reliability issues in terms of mathematics and engineering, as well as an array of repair techniques, based on the authors' long careers in developing memories and low-voltage CMOS circuits. Nanoscale Memory Repair gives a detailed explanation of the various yield models and calculations, as well as various, practical logic and circuits that are critical for higher yield and reliability.

Autoren/Hrsg.

Horiguchi, Masashi

Itoh, Kiyoo

Inhaltsverzeichnis

1;Nanoscale Memory Repair;3
1.1;Preface;5
1.2;Contents;7
1.3;Chapter 1: An Introduction to Repair Techniques;11
1.3.1;1.1 Introduction;11
1.3.2;1.2 Hard and Soft Errors and Repair Techniques;11
1.3.2.1;1.2.1 Hard and Soft Errors;12
1.3.2.2;1.2.2 Redundancy;13
1.3.2.3;1.2.3 ECC;15
1.3.2.4;1.2.4 Combination of Redundancy and ECC;18
1.3.2.5;1.2.5 Others;18
1.3.3;1.3 Margin Errors and Repair Techniques;19
1.3.3.1;1.3.1 Device and Process Variations;21
1.3.3.2;1.3.2 Timing and Voltage Margin Errors;21
1.3.3.3;1.3.3 Reductions of Margin Errors;24
1.3.4;1.4 Speed-Relevant Errors and Repair Techniques;25
1.3.5;References;26
1.4;Chapter 2: Redundancy;28
1.4.1;2.1 Introduction;28
1.4.2;2.2 Models of Fault Distribution;29
1.4.2.1;2.2.1 Poisson Distribution Model;29
1.4.2.2;2.2.2 Negative-Binomial Distribution Model;31
1.4.3;2.3 Yield Improvement Through Redundancy;34
1.4.4;2.4 Replacement Schemes;38
1.4.4.1;2.4.1 Principle of Replacement;38
1.4.4.2;2.4.2 Circuit Implementations;39
1.4.5;2.5 Intrasubarray Replacement;45
1.4.5.1;2.5.1 Simultaneous and Individual Replacement;48
1.4.5.2;2.5.2 Flexible Replacement;51
1.4.5.3;2.5.3 Variations of Intrasubarray Replacement;58
1.4.6;2.6 Intersubarray Replacement;61
1.4.7;2.7 Subarray Replacement;63
1.4.8;2.8 Devices for Storing Addresses;65
1.4.8.1;2.8.1 Fuses;65
1.4.8.2;2.8.2 Antifuses;67
1.4.8.3;2.8.3 Nonvolatile Memory Cells;69
1.4.9;2.9 Testing for Redundancy;70
1.4.10;References;73
1.5;Chapter 3: Error Checking and Correction (ECC);77
1.5.1;3.1 Introduction;77
1.5.2;3.2 Linear Algebra and Linear Codes;78
1.5.2.1;3.2.1 Coding Procedure;78
1.5.2.2;3.2.2 Decoding Procedure;80
1.5.3;3.3 Galois Field;83
1.5.4;3.4 Error-Correcting Codes;85
1.5.4.1;3.4.1 Minimum Distance;86
1.5.4.2;3.4.2 Number of Check Bits;87
1.5.4.3;3.4.3 Single Parity Check Code;90
1.5.4.4;3.4.4 Hamming Code;90
1.5.4.5;3.4.5 Extended Hamming Code and Hsiao Code;92
1.5.4.6;3.4.6 Bidirectional Parity Code;93
1.5.4.7;3.4.7 Cyclic Code;94
1.5.4.8;3.4.8 Nonbinary Code;97
1.5.5;3.5 Coding and Decoding Circuits;100
1.5.5.1;3.5.1 Coding and Decoding Circuits for Hamming Code;100
1.5.5.2;3.5.2 Coding and Decoding Circuits for Cyclic Hamming Code;105
1.5.5.3;3.5.3 Coding and Decoding Circuits for Nonbinary Code;110
1.5.6;3.6 Theoretical Reduction in Soft-Error and Hard-Error Rates;113
1.5.6.1;3.6.1 Reduction in Soft-Error Rate;113
1.5.6.1.1;3.6.1.1 Single-Error Correction;114
1.5.6.1.2;3.6.1.2 Double-Error Correction;115
1.5.6.2;3.6.2 Reduction in Hard-Error Rate;116
1.5.6.2.1;3.6.2.1 Single-Error Correction;116
1.5.6.2.2;3.6.2.2 Double-Error Correction;118
1.5.7;3.7 Application of ECC;119
1.5.7.1;3.7.1 Application to Random-Access Memories;120
1.5.7.1.1;3.7.1.1 ECC Using Bidirectional Parity Code;120
1.5.7.1.2;3.7.1.2 ECC Using (Extended) Hamming Code;123
1.5.7.1.3;3.7.1.3 Multicell Error Problem;127
1.5.7.1.4;3.7.1.4 Partial-Write Problem;130
1.5.7.1.5;3.7.1.5 Startup Problem;133
1.5.7.2;3.7.2 Application to Serial-Access Memories;134
1.5.7.3;3.7.3 Application to Multilevel-Storage Memories;138
1.5.7.4;3.7.4 Application to Other Memories;141
1.5.7.4.1;3.7.4.1 Mask ROMs;141
1.5.7.4.2;3.7.4.2 Content Addressable Memories (CAMs);142
1.5.8;3.8 Testing for ECC;143
1.5.9;References;144
1.6;Chapter 4: Combination of Redundancy and Error Correction;146
1.6.1;4.1 Introduction;146
1.6.2;4.2 Repair of Bit Faults Using Synergistic Effect;146
1.6.2.1;4.2.1 Principle of Synergistic Effect;146
1.6.2.2;4.2.2 Yield Estimation;151
1.6.2.2.1;4.2.2.1 Row Redundancy;151
1.6.2.2.2;4.2.2.2 Column Redundancy;153
1.6.2.2.3;4.2.2.3 Row and Column Redundancies;156
1.6.3;4.3 Application of Synergistic Effect;156
1.6.3.1;4.3.1 Threshold-Voltage Variations;156
1.6.3.2;4.3.2 Estimated Effect;158
1.6.4;References;162
1.7;Chapter 5: Reduction Techniques for Margin Errors of Nanoscale Memories;163
1.7.1;5.1 Introduction;163
1.7.2;5.2 Definition of Vmin;165
1.7.3;5.3 Reduction of Vmin for Wider Margins;166
1.7.3.1;5.3.1 General Features of Vmin;166
1.7.3.1.1;5.3.1.1 MOSFETs Governing Vmin;166
1.7.3.1.2;5.3.1.2 Lowest Necessary Vt (Vt0);169
1.7.3.1.3;5.3.1.3 Parameter gamma;170
1.7.3.1.4;5.3.1.4 Maximum Deviation, DeltaVtmax;170
1.7.3.2;5.3.2 Comparison of Vmin for Logic Block, SRAMs, and DRAMs;171
1.7.4;5.4 Advanced MOSFETs for Wider Margins;171
1.7.4.1;5.4.1 Planar FD-SOI MOSFETs;173
1.7.4.2;5.4.2 FinFETs;175
1.7.5;5.5 Logic Circuits for Wider Margins;179
1.7.5.1;5.5.1 Gate-Source Offset Driving;180
1.7.5.2;5.5.2 Gate-Source Differential Driving;184
1.7.5.3;5.5.3 Combined Driving;186
1.7.5.4;5.5.4 Instantaneous Activation of Low-Vt0 MOSFETs;187
1.7.5.5;5.5.5 Gate Boosting of High-Vt0 MOSFETs;187
1.7.6;5.6 SRAMs for Wider Margins;188
1.7.6.1;5.6.1 Ratio Operations of the 6-T Cell;188
1.7.6.2;5.6.2 Shortening of Datalines and Up-Sizing of the 6-T Cell;189
1.7.6.3;5.6.3 Power Managements of the 6-T Cell;191
1.7.6.4;5.6.4 The 8-T Cell;193
1.7.7;5.7 DRAMs for Wider Margins;194
1.7.7.1;5.7.1 Sensing Schemes;194
1.7.7.2;5.7.2 Vmin(SA) of Sense Amplifier;195
1.7.7.3;5.7.3 Vmin(Cell) of Cell;196
1.7.7.4;5.7.4 Comparison Between Vmin(SA) and Vmin(Cell);196
1.7.7.5;5.7.5 Low-Vt0 Sense Amplifier;197
1.7.7.6;5.7.6 FD-SOI Cells;198
1.7.8;5.8 Subsystems for Wider Margins;200
1.7.8.1;5.8.1 Improvement of Power Supply Integrity;200
1.7.8.2;5.8.2 Reduction in Vt0 at Subsystem Level;201
1.7.8.3;5.8.3 Low-Vt0 Power Switches;202
1.7.9;References;204
1.8;Chapter 6: Reduction Techniques for Speed-Relevant Errors of Nanoscale Memories;208
1.8.1;6.1 Introduction;208
1.8.2;6.2 Reduction Techniques for Speed-Degradation Errors;209
1.8.3;6.3 Reduction Techniques for Interdie Speed-Variation Errors;210
1.8.3.1;6.3.1 On-Chip VBB Compensation;212
1.8.3.2;6.3.2 On-Chip VDD Compensation and Others;216
1.8.4;References;217
1.9;Index;218