Huang Robust Computing with Nano-scale Devices

Progresses and Challenges
1. Auflage 2010
ISBN: 978-90-481-8540-5
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 58, 180 Seiten

Reihe: Lecture Notes in Electrical Engineering

Robust Nano-Computing focuses on various issues of robust nano-computing, defect-tolerance design for nano-technology at different design abstraction levels. It addresses both redundancy- and configuration-based methods as well as fault detecting techniques through the development of accurate computation models and tools. The contents present an insightful view of the ongoing researches on nano-electronic devices, circuits, architectures, and design methods, as well as provide promising directions for future research.

Autoren/Hrsg.

Huang, Chao

Inhaltsverzeichnis

1;Contents;6
2;Introduction;10
3;Fault Tolerant Nanocomputing;15
3.1;Introduction;15
3.2;Principles of Fault Tolerant Nanocomputer Systems;17
3.3;Hardware Redundancy;19
3.3.1;N-Modular Redundancy;19
3.3.2;NAND Multiplexing;21
3.3.3;Reconfiguration;23
3.4;Information Redundancy;26
3.5;Time Redundancy;26
3.6;Coverage;27
3.7;Process Variations in Nanoscale Circuits;28
3.8;Fault Tolerant Nanocomputer Applications;29
3.8.1;General-Purpose Computing;30
3.8.2;Long-Life Applications;30
3.8.3;Critical-Computation Applications;30
3.8.4;High-Availability Applications;31
3.8.5;Maintenance Postponement Applications;31
3.9;Trends and Future;31
3.10;References;32
4;Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics;36
4.1;Introduction;36
4.2;Previous Approaches;38
4.2.1;Defect-Tolerant Techniques;38
4.2.2;Defect Avoidance Techniques;40
4.2.3;Defect-Tolerant FPGA Design Techniques;42
4.2.4;Reliability Analysis;44
4.3;Proposed Defect Tolerance Technique;44
4.4;Experimental Results;49
4.4.1;Stuck-Open and Stuck-Short Defect Analysis;49
4.4.2;Bridging Defect Analysis;52
4.5;Conclusion;53
4.6;References;54
5;Fault-Tolerant Design for Nanowire-Based Programmable Logic Arrays;57
5.1;Introduction;57
5.2;Background;58
5.2.1;Nanowire-Based PLA ;58
5.2.2;Defect Model ;59
5.3;Redundancy-Based Defect-Tolerant Techniques;60
5.3.1;Conventional Redundancy-Based Techniques ;60
5.3.2;Logic Duplication in PLA ;61
5.4;Defect-Aware Logic Mapping for Nanowire-Based PLA;62
5.4.1;Defect-Free Subset Identification ;63
5.4.2;Defect-Aware Mapping Through Bipartite Graph Embedding ;64
5.4.3;SAT-Based Defect-Aware Mapping ;66
5.5;Experimental Results ;70
5.6;Conclusions and Perspectives;73
5.7;References;73
6;Built-In Self-Test and Defect Tolerance for Molecular Electronics-Based NanoFabrics;75
6.1;Introduction;75
6.1.1;NanoFabric Architecture;76
6.1.2;Fault Model;78
6.1.3;Summary of the Proposed Method;79
6.2;Related Prior Work;79
6.3;BIST Procedure;81
6.3.1;Test Architectures (TAs);82
6.3.2;Test Procedure;84
6.4;Test Configurations;85
6.4.1;Test Configurations for Detecting Faults in NanoBlocks;85
6.4.2;Test Configurations for Detecting Faults in SwitchBlocks;88
6.4.3;Number of Test Configurations;91
6.4.4;Time Analysis for BIST;93
6.5;Recovery Analysis;94
6.6;Simulation and Results;96
6.7;Discussion;101
6.8;Conclusion;102
6.9;References;102
7;The Prospect and Challenges of CNFET Based Circuits: A Physical Insight;105
7.1;Introduction;105
7.2;Fundamentals of CNFET;107
7.3;Compact Model of CNFET;109
7.4;Impact of Parasitics on Circuit Performance;113
7.4.1;Geometry Dependent Parasitic Capacitance;114
7.4.2;Analysis of Fringe Capacitance;115
7.5;Impact of Process Variation;118
7.5.1;A Physical Insight to CNFET Characteristics Under Process Variation;118
7.5.2;CNFET Performance Under Process Variation;119
7.5.2.1;Impact on Drive Current;121
7.5.2.2;Impact on Capacitance;123
7.5.2.3;Impact on Circuit Performance;123
7.6;Summary;125
7.7;Appendix I: Polynomial Expression of QCNT;126
7.8;References;127
8;Computing with Nanowires: A Self Assembled Neuromorphic Architecture;130
8.1;Introduction;130
8.2;Self Assembly of Neuromorphic Networks;131
8.3;Electrical Characterization of the Nanowires;132
8.3.1;What Causes the Negative Differential Resistance?;135
8.3.2;Other Electrical Parameters;135
8.4;Simulation Results;137
8.5;Conclusion;141
8.6;References;141
9;Computational Opportunities and CAD for Nanotechnologies;142
9.1;Introduction;142
9.2;A Holistic CAD Platform for Nanotechnologies;144
9.3;High-Level Modeling and Simulation Tool (HLMS);146
9.4;Artificial Ecosystems;149
9.4.1;Spontaneous Creation of Artificial Organisms;149
9.4.2;Optimization of Existing Functions;150
9.4.3;Acquisition of New Functions;150
9.5;Systems of Particles and Emergence of Relativistic Space-Time;151
9.6;Nano-Network Architecture Fit Tool (NAF);152
9.7;Circuit Synthesis Tool (CS);153
9.8;Architectures for Complex Systems Implementation;154
9.8.1;Architectures for Systems Comporting Mobile Modules;154
9.8.2;Generic Communication Architectures for Systems Comprising Mobile Modules;158
9.8.2.1;Associative Computer Approach;158
9.9;Nonconventional Architectures;162
9.9.1;Computational Model of Quantum Systems;162
9.9.2;Implementing Complex Systems Composed of Quantum Objects;166
9.9.3;Quantum Computing;167
9.9.4;CAD for Non-conventional Architectures;174
9.10;Conclusions;175
9.11;References;176
10;Index;179