Buch, Englisch, 248 Seiten, Format (B × H): 175 mm x 250 mm, Gewicht: 614 g
Buch, Englisch, 248 Seiten, Format (B × H): 175 mm x 250 mm, Gewicht: 614 g
ISBN: 978-0-521-86315-5
Verlag: Cambridge University Press
The increasingly demanding performance requirements of communications systems, as well as problems posed by the continued scaling of silicon technology, present numerous challenges for the design of frequency synthesizers in modern transceivers. This book contains everything you need to know for the efficient design of frequency synthesizers for today's communications applications. If you need to optimize performance and minimize design time, you will find this book invaluable. Using an intuitive yet rigorous approach, the authors describe simple analytical methods for the design of phase locked loop (PLL) frequency synthesizers using scaled silicon CMOS and bipolar technologies. The entire design process, from system-level specification to layout, is covered comprehensively. Practical design examples are included, and implementation issues are addressed. A key problem-solving resource for practitioners in IC design, the book will also be of interest to researchers and graduate students in electrical engineering.
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Weitere Infos & Material
Preface; 1. Local oscillator requirements; 2. Phase-Locked Loops; 3. Fractional-N PLLs; 4. Electronic oscillators; 5. Noise in Oscillators; 6.Reactive components in oscillators; 7. Noise up-conversion in VCOs; 8. Frequency division; 9. Phase Comparison; Index.