Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

1. Auflage. Softcover version of original hardcover Auflage 2008
ISBN: 978-1-4419-4554-9
Verlag: Springer US

Buch, Englisch, 302 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 511 g

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

Zielgruppe

Research

Autoren/Hrsg.

Mohanty, Saraju P.

Patra, Priyardarsan

Ranganathan, Nagarajan

Kougianos, Elias

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

High-Level Synthesis Fundamentals.- Power Modeling and Estimation at Transistor and Logic Gate Levels.- Architectural Power Modeling and Estimation.- Power Reduction Fundamentals.- Energy or Average Power Reduction.- Peak Power Reduction.- Transient Power Reduction.- Leakage Power Reduction.- Conclusions and Future Direction.