Patterson / Hennessy Computer Organization and Design, Revised Printing

The Hardware/Software Interface
3. Auflage 2007
ISBN: 978-0-08-055033-6
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 741 Seiten, Web PDF

Reihe: Morgan Kaufmann

What's New in the Third Edition, Revised Printing
The same great book gets better! This revised printing features all of the original content along with these additional features:
• Appendix A (Assemblers, Linkers, and the SPIM Simulator) has been moved from the CD-ROM into the printed book
• Corrections and bug fixes
Third Edition features
New pedagogical features
•Understanding Program Performance
-Analyzes key performance issues from the programmer's perspective
•Check Yourself Questions
-Helps students assess their understanding of key points of a section
•Computers In the Real World
-Illustrates the diversity of applications of computing technology beyond traditional desktop and servers
•For More Practice
-Provides students with additional problems they can tackle
•In More Depth
-Presents new information and challenging exercises for the advanced student

New reference features
•Highlighted glossary terms and definitions appear on the book page, as bold-faced entries in the index, and as a separate and searchable reference on the CD.
•A complete index of the material in the book and on the CD appears in the printed index and the CD includes a fully searchable version of the same index.
•Historical Perspectives and Further Readings have been updated and expanded to include the history of software R&D.
•CD-Library provides materials collected from the web which directly support the text.
In addition to thoroughly updating every aspect of the text to reflect the most current computing technology, the third edition
•Uses standard 32-bit MIPS 32 as the primary teaching ISA.
•Presents the assembler-to-HLL translations in both C and Java.
•Highlights the latest developments in architecture in Real Stuff sections:
-Intel IA-32
-Power PC 604
-Google's PC cluster
-Pentium P4
-SPEC CPU2000 benchmark suite for processors
-SPEC Web99 benchmark for web servers
-EEMBC benchmark for embedded systems
-AMD Opteron memory hierarchy
-AMD vs. 1A-64
New support for distinct course goals
Many of the adopters who have used our book throughout its two editions are refining their courses with a greater hardware or software focus. We have provided new material to support these course goals:
New material to support a Hardware Focus
•Using logic design conventions
•Designing with hardware description languages
•Advanced pipelining
•Designing with FPGAs
•HDL simulators and tutorials
•Xilinx CAD tools
New material to support a Software Focus
•How compilers work
•How to optimize compilers
•How to implement object oriented languages
•MIPS simulator and tutorial
•History sections on programming languages, compilers, operating systems and databases
On the CD
•NEW: Search function to search for content on both the CD-ROM and the printed text
•CD-Bars: Full length sections that are introduced in the book and presented on the CD
•CD-Appendixes: Appendices B-D
•CD-Library: Materials collected from the web which directly support the text
•CD-Exercises: For More Practice provides exercises and solutions for self-study
•In More Depth presents new information and challenging exercises for the advanced or curious student
•Glossary: Terms that are defined in the text are collected in this searchable reference
•Further Reading: References are organized by the chapter they support
•Software: HDL simulators, MIPS simulators, and FPGA design tools
•Tutorials: SPIM, Verilog, and VHDL
•Additional Support: Processor Models, Labs, Homeworks, Index covering the book and CD contents
Instructor Support

David A. Patterson has been teaching computer architecture at the University of California, Berkeley, since joining the faculty in 1977, where he holds the Pardee Chair of Computer Science. His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.

Autoren/Hrsg.

Patterson, David A.

Hennessy, John L.

Inhaltsverzeichnis

1;Front cover;1
2;Title page;4
3;Copyright page;5
4;Table of Contents;6
5;Preface;12
5.1;About This Book;12
5.2;About the Other Book;12
5.3;Changes for the Third Edition;13
5.4;Instructor Support;16
5.5;Concluding Remarks;16
5.6;Acknowledgments for the Third Edition;16
6;1 Computer Abstractions and Technology;19
6.1;1.1 Introduction;20
6.1.1;Classes of Computing Applications and Their Characteristics;22
6.1.2;What You Can Learn in This Book;25
6.2;1.2 Below Your Program;28
6.2.1;From a High-Level Language to the Language of Hardware;29
6.3;1.3 Under the Covers;32
6.3.1;Anatomy of a Mouse;33
6.3.2;Through the Looking Glass;35
6.3.3;Opening the Box;35
6.3.4;A Safe Place for Data;40
6.3.5;Communicating with Other Computers;42
6.3.6;Technologies for Building Processors and Memory;44
6.4;1.4 Real Stuff: Manufacturing Pentium 4 Chips;45
6.5;1.5 Fallacies and Pitfalls;50
6.5.1;Road Map for This Book;52
6.6;1.6 Concluding Remarks;52
6.7;1.7 Historical Perspective and Further Reading;53
6.8;1.8 Exercises;53
6.9;Computers in the Real World;61
7;2 Instructions: Language of the Computer;63
7.1;2.1 Introduction;65
7.2;2.2 Operations of the Computer Hardware;66
7.3;2.3 Operands of the Computer Hardware;69
7.3.1;Memory Operands;71
7.3.2;Constant or Immediate Operands;74
7.4;2.4 Representing Instructions in the Computer;77
7.4.1;MIPS Fields;80
7.5;2.5 Logical Operations;85
7.6;2.6 Instructions for Making Decisions;89
7.6.1;Loops;91
7.6.2;Case/Switch Statement;93
7.7;2.7 Supporting Procedures in Computer Hardware;96
7.7.1;Using More Registers;97
7.7.2;Nested Procedures;100
7.7.3;Allocating Space for New Data on the Stack;103
7.7.4;Allocating Space for New Data on the Heap;104
7.8;2.8 Communicating with People;107
7.8.1;Characters and Strings in Java;110
7.8.2;32-Bit Immediate Operands;112
7.9;2.9 MIPS Addressing for 32-Bit Immediates and Addresses;112
7.9.1;Addressing in Branches and Jumps;114
7.9.2;MIPS Addressing Mode Summary;117
7.9.3;Decoding Machine Language;117
7.10;2.10 Translating and Starting a Program;123
7.10.1;Compiler;124
7.10.2;Assembler;124
7.10.3;Linker;125
7.10.4;Loader;129
7.10.5;Dynamically Linked Libraries;129
7.10.6;Starting a Java Program;131
7.10.7;High-Level Optimizations;133
7.11;2.11 How Compilers Optimize;133
7.11.1;Local and Global Optimizations;134
7.12;2.12 How Compilers Work: An Introduction;138
7.13;2.13 A C Sort Example to Put It All Together;138
7.13.1;The Procedure;139
7.13.2;Array Version of Clear;147
7.14;2.14 Implementing an Object-Oriented Language;147
7.15;2.15 Arrays versus Pointers;147
7.15.1;Pointer Version of Clear;149
7.15.2;Comparing the Two Versions of Clear;150
7.16;2.16 Real Stuff: IA-32 Instructions;151
7.16.1;The Intel IA-32;151
7.16.2;IA-32 Integer Operations;155
7.16.3;IA-32 Instruction Encoding;157
7.16.4;IA-32 Conclusion;159
7.17;2.17 Fallacies and Pitfalls;160
7.18;2.18 Concluding Remarks;162
7.19;2.19 Historical Perspective and Further Reading;164
7.20;2.20 Exercises;164
7.21;Computers in the Real World;173
8;3 Arithmetic for Computers;175
8.1;3.1 Introduction;177
8.2;3.2 Signed and Unsigned Numbers;177
8.2.1;Summary;185
8.3;3.3 Addition and Subtraction;187
8.3.1;Summary;191
8.4;3.4 Multiplication;193
8.4.1;Sequential Version of the Multiplication Algorithm and Hardware;194
8.4.2;Signed Multiplication;197
8.4.3;Faster Multiplication;198
8.4.4;Multiply in MIPS;198
8.4.5;Summary;198
8.5;3.5 Division;200
8.5.1;A Division Algorithm and Hardware;201
8.5.2;Signed Division;204
8.5.3;Faster Division;205
8.5.4;Divide in MIPS;205
8.5.5;Summary;206
8.6;3.6 Floating Point;206
8.6.1;Floating-Point Representation;208
8.6.2;Floating-Point Addition;214
8.6.3;Floating-Point Multiplication;219
8.6.4;Floating-Point Instructions in MIPS;223
8.6.5;Accurate Arithmetic;230
8.6.6;Summary;232
8.7;3.7 Real Stuff: Floating Point in the IA-32;234
8.7.1;The IA-32 Floating-Point Architecture;235
8.7.2;The Intel Streaming SIMD Extension 2 (SSE2) Floating-Point Architecture;237
8.8;3.8 Fallacies and Pitfalls;237
8.9;3.9 Concluding Remarks;242
8.10;3.10 Historical Perspective and Further Reading;246
8.11;3.11 Exercises;246
8.12;Computers in the Real World;253
9;4 Assessing and Understanding Performance;255
9.1;4.1 Introduction;257
9.1.1;Defining Performance;258
9.1.2;Measuring Performance;261
9.2;4.2 CPU Performance and Its Factors;263
9.3;4.3 Evaluating Performance;271
9.3.1;Comparing and Summarizing Performance;273
9.3.2;Total Execution Time: A Consistent Summary Measure;274
9.3.3;Performance with SPEC CPU Benchmarks;276
9.4;4.4 Real Stuff: Two SPEC Benchmarks and the Performance of Recent Intel Processors;276
9.4.1;SPECweb99: A Throughput Benchmark for Web Servers;279
9.4.2;Performance, Power, and Energy Efficiency;280
9.5;4.5 Fallacies and Pitfalls;283
9.6;4.6 Concluding Remarks;287
9.7;4.7 Historical Perspective and Further Reading;289
9.8;4.8 Exercises;289
9.9;Computers in the Real World;297
10;5 The Processor: Datapath and Control;299
10.1;5.1 Introduction;301
10.1.1;A Basic MIPS Implementation;302
10.2;5.2 Logic Design Conventions;306
10.3;5.3 Building a Datapath;309
10.3.1;Creating a Single Datapath;315
10.4;5.4 A Simple Implementation Scheme;317
10.4.1;The ALU Control;318
10.4.2;Designing the Main Control Unit;320
10.4.3;Why a Single-Cycle Implementation Is Not Used Today;331
10.5;5.5 A Multicycle Implementation;335
10.5.1;Breaking the Instruction Execution into Clock Cycles;342
10.5.2;Defining the Control;347
10.6;5.6 Exceptions;357
10.6.1;How Exceptions Are Handled;358
10.6.2;How Control Checks for Exceptions;360
10.7;5.7 Microprogramming: Simplifying Control Design;363
10.8;5.8 An Introduction to Digital Design Using a Hardware Design Language;363
10.8.1;Challenges Implementing More Complex Architectures;364
10.9;5.9 Real Stuff: The Organization of Recent Pentium Implementations;364
10.9.1;The Structure of the Pentium 4 Implementation;365
10.10;5.10 Fallacies and Pitfalls;367
10.11;5.11 Concluding Remarks;369
10.12;5.12 Historical Perspective and Further Reading;370
10.13;5.13 Exercises;371
10.14;Computers in the Real World;383
11;6 Enhancing Performance with Pipelining;385
11.1;6.1 An Overview of Pipelining;387
11.1.1;Designing Instruction Sets for Pipelining;391
11.1.2;Pipeline Hazards;392
11.1.3;Pipeline Overview Summary;400
11.2;6.2 A Pipelined Datapath;401
11.2.1;Graphically Representing Pipelines;412
11.3;6.3 Pipelined Control;416
11.4;6.4 Data Hazards and Forwarding;419
11.5;6.5 Data Hazards and Stalls;430
11.6;6.6 Control Hazards;433
11.6.1;Assume Branch Not Taken;435
11.6.2;Reducing the Delay of Branches;435
11.6.3;Dynamic Branch Prediction;438
11.6.4;Pipeline Summary;441
11.7;6.7 Using a Hardware Description Language to Describe and Model a Pipeline;443
11.8;6.8 Exceptions;444
11.9;6.9 Advanced Pipelining: Extracting More Performance;449
11.9.1;The Concept of Speculation;451
11.9.2;Static Multiple Issue;452
11.9.3;Dynamic Multiple-Issue Processors;459
11.10;6.10 Real Stuff: The Pentium 4 Pipeline;465
11.11;6.11 Fallacies and Pitfalls;468
11.12;6.12 Concluding Remarks;469
11.13;6.13 Historical Perspective and Further Reading;471
11.14;6.14 Exercises;471
11.15;Computers in the Real World;481
12;7 Large and Fast: Exploiting Memory Hierarchy;483
12.1;7.1 Introduction;485
12.2;7.2 The Basics of Caches;490
12.2.1;Accessing a Cache;493
12.2.2;Handling Cache Misses;499
12.2.3;Handling Writes;500
12.2.4;An Example Cache: The Intrinsity FastMATH Processor;502
12.2.5;Designing the Memory System to Support Caches;504
12.2.6;Summary;508
12.3;7.3 Measuring and Improving Cache Performance;509
12.3.1;Reducing Cache Misses by More Flexible Placement of Blocks;513
12.3.2;Locating a Block in the Cache;519
12.3.3;Choosing Which Block to Replace;521
12.3.4;Reducing the Miss Penalty Using Multilevel Caches;521
12.3.5;Check Yourself;526
12.3.6;Summary;527
12.4;7.4 Virtual Memory;528
12.4.1;Placing a Page and Finding It Again;532
12.4.2;Page Faults;533
12.4.3;What about Writes?;538
12.4.4;Making Address Translation Fast: The TLB;538
12.4.5;Integrating Virtual Memory, TLBs, and Caches;541
12.4.6;Implementing Protection with Virtual Memory;545
12.4.7;Handling TLB Misses and Page Faults;548
12.4.8;Summary;553
12.4.9;Question 1: Where Can a Block Be Placed?;555
12.5;7.5 A Common Framework for Memory Hierarchies;555
12.5.1;Question 2: How Is a Block Found?;557
12.5.2;Question 3: Which Block Should Be Replaced on a Cache Miss?;558
12.5.3;Question 4: What Happens on a Write?;559
12.5.4;The Three Cs: An Intuitive Model for Understanding the Behavior of Memory Hierarchies;560
12.5.5;Check Yourself;562
12.6;7.6 Real Stuff: The Pentium P4 and the AMD Opteron Memory Hierarchies;563
12.6.1;The Memory Hierarchies of the P4 and Opteron;564
12.6.2;Techniques to Reduce Miss Penalties;564
12.7;7.7 Fallacies and Pitfalls;567
12.8;7.8 Concluding Remarks;569
12.8.1;Recent Trends;570
12.9;7.9 Historical Perspective and Further Reading;572
12.10;7.10 Exercises;572
12.10.1;Answers to Check Yourself;578
12.11;Computers in the Real World;579
13;8 Storage, Networks, and Other Peripherals;581
13.1;8.1 Introduction;583
13.2;8.2 Disk Storage and Dependability;586
13.2.1;Dependability, Reliability, and Availability;588
13.2.2;RAID;591
13.3;8.3 Networks;597
13.3.1;Bus Basics;598
13.4;8.4 Buses and Other Connections between Processors, Memory, and I/O Devices;598
13.4.1;The Buses and Networks of the Pentium 4;602
13.5;8.5 Interfacing I/O Devices to the Processor, Memory, and Operating System;605
13.5.1;Giving Commands to I/O Devices;606
13.5.2;Communicating with the Processor;607
13.5.3;Interrupt Priority Levels;608
13.5.4;Transferring the Data between a Device and Memory;610
13.5.5;Direct Memory Access and the Memory System;612
13.6;8.6 I/O Performance Measures: Examples from Disk and File Systems;614
13.6.1;Transaction Processing I/O Benchmarks;615
13.6.2;File System and Web I/O Benchmarks;615
13.6.3;I/O Performance versus Processor Performance;616
13.7;8.7 Designing an I/O System;617
13.8;8.8 Real Stuff: A Digital Camera;620
13.9;8.9 Fallacies and Pitfalls;623
13.10;8.10 Concluding Remarks;626
13.11;8.11 Historical Perspective and Further Reading;628
13.12;8.12 Exercises;628
13.13;Computers in the Real World;639
14;Appendix A Assemblers, Linkers, and the SPIM Simulator;641
14.1;A.1 Introduction;642
14.1.1;When to Use Assembly Language;647
14.1.2;Drawbacks of Assembly Language;648
14.2;A.2 Assemblers;649
14.2.1;Object File Format;652
14.2.2;Additional Facilities;653
14.3;A.3 Linkers;657
14.4;A.4 Loading;658
14.5;A.5 Memory Usage;659
14.6;A.6 Procedure Call Convention;661
14.6.1;Procedure Calls;662
14.6.2;Procedure Call Example;665
14.6.3;Another Procedure Call Example;669
14.7;A.7 Exceptions and Interrupts;672
14.8;A.8 Input and Output;676
14.8.1;Simulation of a Virtual Machine;679
14.9;A.9 SPIM;679
14.9.1;Getting Started with SPIM;680
14.9.2;Surprising Features;681
14.9.3;Byte Order;681
14.9.4;System Calls;682
14.9.5;Addressing Modes;683
14.10;A.10 MIPS R2000 Assembly Language;683
14.10.1;Assembler Syntax;685
14.10.2;Encoding MIPS Instructions;687
14.10.3;Instruction Format;687
14.10.4;Arithmetic and Logical Instructions;689
14.10.5;Constant-Manipulating Instructions;695
14.10.6;Comparison Instructions;695
14.10.7;Branch Instructions;697
14.10.8;Jump Instructions;701
14.10.9;Trap Instructions;701
14.10.10;Load Instructions;703
14.10.11;Store Instructions;705
14.10.12;Data Movement Instructions;707
14.10.13;Floating-Point Instructions;710
14.10.14;Exception and Interrupt Instructions;717
14.10.15;Further Reading;718
14.11;A.11 Concluding Remarks;718
14.12;A.12 Exercises;719
15;Index;722
16;MIPS Reference Data;738