Platzner / Wehn / Teich Dynamically Reconfigurable Systems

Architectures, Design Methods and Applications
1. Auflage 2010
ISBN: 978-90-481-3485-4
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 441 Seiten

Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems. Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.

Autoren/Hrsg.

Platzner, Marco

Teich, Jürgen

Wehn, Norbert

Inhaltsverzeichnis

1;Foreword;5
2;Preface;7
3;Contents;10
4;Contributors;20
5;Part I Architectures;25
5.1;Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns;26
5.1.1;Introduction;26
5.1.2;HoneyComb Architecture;28
5.1.2.1;Architectural Considerations;28
5.1.2.2;HoneyComb Overview;31
5.1.2.3;Communication Network and Online Adaptive Routing Technique;32
5.1.2.4;Datapath Cells (DPHC);34
5.1.2.5;Memory Cells (MEMHC);36
5.1.2.6;Input/Output Cells (IOHC);36
5.1.2.7;Power Saving Techniques;38
5.1.3;Tool Support;38
5.1.3.1;HoneyComb Assembler and the Hierarchical Programming Model;39
5.1.3.2;HoneyComb Language (HCL) and Compiler;40
5.1.3.3;Debugging Tool-HoneyComb Viewer;41
5.1.3.4;Super-Configuration Generator, Configuration Editor and Configuration Manager;41
5.1.3.5;Hierarchy Generator;42
5.1.3.6;Application and Synthesis Results;42
5.1.4;Future Work;45
5.1.5;Conclusion;46
5.1.6;References;46
5.2;Reconfigurable Components for Application-Specific Processor Architectures;48
5.2.1;Introduction;48
5.2.2;Parameterized eFPGA Target Architecture;50
5.2.3;Physical Implementation of Application Class Specific eFPGAs;55
5.2.4;Mapping and Configuration;58
5.2.5;Examples of (Stand Alone) eFPGAs as SoC Building Blocks;60
5.2.6;Examples of eFPGAs as Coprocessors to Standard RISC Processor Kernels;62
5.2.6.1;General-Purpose Processors Coupled with eFPGAs;64
5.2.6.2;ASIPs Coupled with eFPGA-Based Accelerators;64
5.2.6.2.1;ASIP;64
5.2.6.2.2;ASIP-eFPGA Coupling Mechanisms;65
5.2.6.2.3;Performance and Cost Evaluation;67
5.2.6.2.4;Examples of eFPGAs as Coprocessors to Application Specific Instruction Processors (rASIPs);68
5.2.7;Conclusion;69
5.2.8;References;70
5.3;Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform;73
5.3.1;Introduction;74
5.3.2;Drawbacks of Existing Dynamically Reconfigurable Systems;74
5.3.3;The Erlangen Slot Machine;77
5.3.3.1;Architecture Overview;77
5.3.3.2;The BabyBoard;78
5.3.3.2.1;Computation and Reconfigurable Engine;78
5.3.3.2.2;The Reconfiguration Manager;79
5.3.3.2.3;Memory;79
5.3.3.2.4;Debug Lines;80
5.3.3.3;The MotherBoard;80
5.3.4;Inter-module Communication;81
5.3.4.1;Communication Between Adjacent Modules;82
5.3.4.2;Communication via Shared Memory;82
5.3.4.3;Communication via RMB;82
5.3.4.4;Communication via the Crossbar;83
5.3.5;Reconfiguration Manager;84
5.3.5.1;Flexible Plugin Architecture;84
5.3.5.2;Reconfiguration Scenarios;86
5.3.5.3;Implementation Results;86
5.3.6;Case Study: Video and Audio Streaming;87
5.3.7;Usage of the ESM in Different Fields;89
5.3.8;Conclusions;91
5.3.9;References;92
6;Part II Design Methods and Tools-Modeling, Evaluation and Compilation;94
6.1;Models and Algorithms for Hyperreconfigurable Hardware;95
6.1.1;Introduction;95
6.1.2;Hyperreconfigurable Machines;96
6.1.2.1;2-level Reconfiguration;96
6.1.2.2;Multi-level Reconfiguration;100
6.1.2.3;Heterogeneous Multi-level Reconfiguration;100
6.1.3;Example Architectures and Test Cases;101
6.1.3.1;Fine-granular Hyperreconfigurable Machine;101
6.1.3.2;Coarse-granular Hyperreconfigurable Machine;102
6.1.4;The Partition into Hypercontexts Problem;103
6.1.4.1;Experiments and Results;104
6.1.5;Diverse Granularity in Multi-level Reconfigurable Systems;106
6.1.6;Partial Reconfiguration and Hyperreconfiguration;110
6.1.6.1;Frame Model of Partially Reconfigurable Architectures;110
6.1.6.2;Results;112
6.1.7;Conclusions;113
6.1.8;References;113
6.2;Evaluation and Design Methods for Processor-Like Reconfigurable Architectures;115
6.2.1;Introduction;115
6.2.2;Benefits and Costs of Processor-Like Reconfiguration;117
6.2.2.1;CRC Model;117
6.2.2.2;Compiler;119
6.2.2.3;Evaluation;120
6.2.3;Specialization/Instruction Set Extension;122
6.2.3.1;Methodology;124
6.2.3.2;Study Case: Multipoint FFT for Scalable OFDMA Based Systems;125
6.2.4;Optimizing Power;128
6.2.4.1;Optimizing Power by Instruction Set Extensions;128
6.2.4.2;Optimizing Power by Dual-VDD Architectures;128
6.2.4.2.1;The Dual-VDD Architecture Model;129
6.2.4.2.2;Delay and Area;130
6.2.4.2.3;Power Estimation;130
6.2.5;Optimizing External Reconfiguration;131
6.2.5.1;Multi-Context Configuration Prefetching;132
6.2.5.2;Speculative Configuration Prefetching;133
6.2.5.3;Experimental Results;134
6.2.6;Conclusion;135
6.2.7;References;135
6.3;Adaptive Computing Systems and Their Design Tools;137
6.3.1;Introduction;137
6.3.2;Execution Model;138
6.3.3;ACS Architecture;140
6.3.3.1;Reconfigurable System-on-Chip Architecture;140
6.3.3.2;Operating System Integration;141
6.3.3.2.1;RCU-SPP Signalling;142
6.3.3.2.2;Shared Virtual Memory;143
6.3.3.3;Evaluation;145
6.3.4;Hardware/Software Co-compilation Flow;145
6.3.4.1;Overview;145
6.3.4.2;Profile-Based Inlining and Partitioning;146
6.3.4.3;CMDFG Intermediate Representation;147
6.3.4.4;CoCoMa Controller Model;149
6.3.5;Infrastructure;151
6.3.5.1;Parametrized Module Library;151
6.3.5.2;Physical Design Aspects;151
6.3.5.3;Reconfiguration Scheduling;153
6.3.6;Lessons Learned;154
6.3.7;Future Work;156
6.3.8;Conclusions;156
6.3.9;References;157
6.4;PolyDyn-Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs;159
6.4.1;Introduction;159
6.4.2;Related Work;161
6.4.3;Methodology;162
6.4.3.1;General Concept;163
6.4.3.2;Lifetime and Conflict Management;165
6.4.4;Derived Interface Classes;167
6.4.5;Modelling Example: Car Audio System;168
6.4.5.1;Coding Style: From C++ Polymorphism to OSSS+R;169
6.4.5.1.1;Devices and Timing;171
6.4.5.2;Simulation;172
6.4.6;Synthesising OSSS+R;173
6.4.6.1;From OSSS+R to RT Level;173
6.4.6.1.1;Recon-Object;175
6.4.6.1.2;Reconfiguration Controller;175
6.4.6.1.3;Method Calls;175
6.4.6.1.4;RTL Simulation Model;175
6.4.6.1.5;From RTL to Bitstreams;176
6.4.7;Evaluation;176
6.4.8;Conclusion and Future Work;177
6.4.9;References;177
7;Part III Design Methods and Tools-Optimization and Runtime Systems;179
7.1;Design Methods and Tools for Improved Partial Dynamic Reconfiguration;180
7.1.1;Introduction;180
7.1.2;Motivation;182
7.1.3;Reconfigurable Module Architecture and Partitioning;183
7.1.4;Reconfiguration State Graph;184
7.1.5;Module Mapping and Virtual Architecture;185
7.1.6;High-Level Synthesis of Reconfigurable Modules;187
7.1.6.1;Resource Type Binding;188
7.1.6.2;Resource Instance Binding;189
7.1.6.3;Control Generation;191
7.1.7;Experiments;192
7.1.7.1;Experimental Setup;192
7.1.7.1.1;Resource Type Binding Methods;192
7.1.7.1.2;Resource Instance Binding Methods;192
7.1.7.1.3;Implementation Scenarios;192
7.1.7.1.4;Benchmark Characteristics;193
7.1.7.2;Benchmark Results and Discussion;193
7.1.8;System Design for Efficient Partial Dynamic Reconfiguration;197
7.1.9;References;199
7.2;Dynamic Partial Reconfiguration by Means of Algorithmic Skeletons-A Case Study;201
7.2.1;Introduction;201
7.2.2;Overview of the Overall System;203
7.2.3;Library of Algorithmic Skeletons;206
7.2.3.1;Algorithmic Skeletons for Defining the Structure of the Design;206
7.2.3.2;Algoskels;207
7.2.3.3;Algorithmic Skeletons for Partial Reconfigurable Systems;208
7.2.4;Application Scenario: Channel Vocoder Analyzer;209
7.2.5;Conclusion;215
7.2.6;References;215
7.3;ReCoNodes-Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices;217
7.3.1;Introduction;217
7.3.2;Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device;219
7.3.2.1;Two-dimensional Strip Packing;221
7.3.2.2;Defragmentation Approach and Computational Results;222
7.3.2.3;Online Packing;222
7.3.3;Minimizing Communication Cost for Reconfigurable Slot Modules;224
7.3.3.1;Mathematical Model;225
7.3.3.1.1;Minimizing the Number of Parallel Segments;226
7.3.3.1.2;Minimize Segment-Constrained Bandwidth;227
7.3.3.2;Case Study and Results;228
7.3.4;No-break Dynamic Defragmentation of Reconfigurable Devices;229
7.3.4.1;Model and Problem Description;230
7.3.4.2;Problem Complexity and Moderate Densities;231
7.3.4.3;A Heuristic Method;231
7.3.5;Scheduling Dynamic Resource Requests;232
7.3.5.1;An ILP;233
7.3.5.2;Heuristic Methods;235
7.3.6;References;237
7.4;ReCoNets-Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections;240
7.4.1;Introduction;240
7.4.2;System Model;242
7.4.3;A Distributed Operating System Architecture for Networked Embedded Systems;243
7.4.3.1;Self-healing and Self-adaptiveness;244
7.4.3.1.1;Discrete Diffusion-Based Task Binding;246
7.4.3.1.2;Replica Placement;248
7.4.3.2;Hardware/Software Task Migration;251
7.4.3.3;Hardware/Software Morphing;252
7.4.3.4;Hardware/Software Checkpointing;254
7.4.4;Design and Synthesis of ReCoNets;255
7.4.4.1;Design Space Exploration;255
7.4.4.2;Dependability Analysis;256
7.4.5;Demonstrator;257
7.4.6;References;259
7.5;Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies;261
7.5.1;Introduction;262
7.5.2;Partial and Dynamic Reconfiguration;263
7.5.2.1;One-dimensional Dynamic and Partial Reconfigurable System Architecture;263
7.5.2.1.1;LUT Based Communication Primitives;264
7.5.2.1.2;Physically Realized Two-dimensional System Approach;266
7.5.3;Network on Chip;266
7.5.3.1;Router Base Modules for the On-line Placement;266
7.5.3.2;Switch for 2D Mesh Based NoC Approach;268
7.5.3.2.1;Switch Layout;268
7.5.3.2.2;Controlling the Switch;269
7.5.4;On Demand System Adaption;269
7.5.4.1;Physical on Line Routing of Communication Structures;269
7.5.4.2;Physical On-line Routing of Parameterizable Filter Modules;270
7.5.5;System Modelling;271
7.5.6;Tool Chain;273
7.5.7;Model Debugging;275
7.5.7.1;Problem;275
7.5.7.2;Debugging Flow;275
7.5.7.3;Interface and Architecture;276
7.5.8;Test;278
7.5.9;Conclusions;279
7.5.10;References;281
7.6;ReconOS: An Operating System for Dynamically Reconfigurable Hardware;284
7.6.1;Introduction;284
7.6.2;Related Work;285
7.6.3;Programming Model;286
7.6.3.1;Hardware Threads;288
7.6.3.2;Thread Creation and Termination;288
7.6.4;Run-Time System;289
7.6.4.1;Hardware Architecture;290
7.6.4.1.1;The Operating System Interface;290
7.6.4.1.1.1;Thread Supervision and Control;291
7.6.4.1.1.2;OS Call Relaying;292
7.6.4.1.1.3;Data Communication Routing;292
7.6.4.2;Hardware Multitasking;293
7.6.4.3;Software Architecture;293
7.6.4.3.1;Delegate Threads;294
7.6.4.3.2;Hardware Scheduler;294
7.6.5;Implementation;295
7.6.5.1;Target Platforms;295
7.6.5.2;Prototypes;295
7.6.5.2.1;ReconOS/eCos;296
7.6.5.2.2;ReconOS/Linux;298
7.6.5.3;Debugging and Monitoring;298
7.6.6;Experimental Measurements;299
7.6.6.1;Application Case Studies;301
7.6.7;Conclusion and Outlook;303
7.6.8;References;303
8;Part IV Applications;306
8.1;FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems;307
8.1.1;Introduction;307
8.1.2;Channel Codes;309
8.1.2.1;Convolutional Codes;310
8.1.2.2;Turbo Codes;310
8.1.2.3;LDPC Codes;311
8.1.3;Decoder Requirements;313
8.1.4;ASIP Design Methodologies;313
8.1.5;Architecture;314
8.1.5.1;General Considerations;314
8.1.5.2;Memory Concept;316
8.1.5.3;Pipeline;317
8.1.5.4;Dynamically Reconfigurable Channel Code Control;318
8.1.5.5;Instruction Set;320
8.1.6;ASIP Validation;322
8.1.7;Results;324
8.1.8;References;327
8.2;Dynamically Reconfigurable Systems for Wireless Sensor Networks;329
8.2.1;Introduction;329
8.2.1.1;Outline;330
8.2.2;Motivation and Background;330
8.2.3;Design of a Reconfigurable Function Unit;331
8.2.3.1;Functional Coverage of the RFU;332
8.2.3.2;The RFU Data Path;332
8.2.4;Dynamic Reconfiguration;334
8.2.4.1;Intra-task Reconfiguration;334
8.2.4.1.1;The Multi-context Configuration Table;334
8.2.4.1.2;Run Control via Tag-matching;336
8.2.4.2;Inter-task Reconfiguration;337
8.2.5;General System Architecture;338
8.2.6;Evaluation Results;339
8.2.6.1;Test Settings;340
8.2.6.2;Synthesis Results;340
8.2.6.3;Evaluation of Energy Efficiency;340
8.2.6.3.1;Reconfiguration Overhead;341
8.2.6.3.2;Comparison of Alternative Reconfiguration Mechanisms;341
8.2.6.3.3;Reconfiguration Power;342
8.2.6.3.4;Architecture Comparison;344
8.2.7;Prototyping of the Sensor Node System;345
8.2.8;Generalisation of the Results;346
8.2.9;Conclusion;346
8.2.10;References;347
8.3;DynaCORE-Dynamically Reconfigurable Coprocessor for Network Processors;349
8.3.1;Introduction;349
8.3.2;Network Processors;350
8.3.2.1;Requirements;351
8.3.3;System Architecture;352
8.3.4;Model;353
8.3.4.1;Principles of Theory;354
8.3.4.2;Modelling DynaCORE;354
8.3.4.3;Simulation;355
8.3.5;Runtime Adaptive Network-on-Chip;357
8.3.5.1;Architecture;358
8.3.5.2;Runtime Adaptation;359
8.3.5.3;Fault Tolerance;359
8.3.6;Reconfiguration Management;360
8.3.6.1;Basic Method;361
8.3.6.2;Optimised Approach;361
8.3.7;Technical Aspects;364
8.3.8;Evaluation;365
8.3.9;Summary;367
8.3.10;References;367
8.4;FlexPath NP-Flexible, Dynamically Reconfigurable Processing Paths in Network Processors;369
8.4.1;Introduction;369
8.4.2;FlexPath NP Concept;371
8.4.2.1;Application Dependent Path Decision;372
8.4.2.2;Load Dependent Path Decision;373
8.4.3;Formal Analysis;374
8.4.4;Simulative Exploration;375
8.4.4.1;FlexPath NP Architecture Evaluation;376
8.4.4.2;Load Balancing in FlexPath NP;377
8.4.5;FPGA Demonstrator;378
8.4.5.1;Architecture;378
8.4.5.2;Experiments;381
8.4.5.2.1;Demonstrator Setup;381
8.4.5.2.2;Single Data Plane CPU (Scenarios 1 and 2);382
8.4.5.2.3;Two Data Plane CPUs (Scenarios 3 and 4);383
8.4.5.2.4;AutoRoute (Scenario 5);385
8.4.5.2.5;DynaCORE (Scenario 6);386
8.4.6;Conclusion;386
8.4.7;References;387
8.5;AutoVision-Reconfigurable Hardware Acceleration for Video-Based Driver Assistance;389
8.5.1;Introduction;389
8.5.1.1;State of the Art & Related Work;391
8.5.1.2;Typical Scenario & Hardware Accelerators;392
8.5.2;AutoVision Architecture;394
8.5.2.1;The AddressEngine-A Pixel Processing Pipeline;395
8.5.3;Fast Dynamic Partial Reconfiguration;397
8.5.3.1;Motivation for Fast Reconfiguration;397
8.5.3.1.1;Inter Video Frame Reconfiguration;397
8.5.3.1.2;Intra Video Frame Reconfiguration;398
8.5.3.2;Bitstream Modification;398
8.5.3.2.1;Combitgen;398
8.5.3.3;Hardware Modification;400
8.5.3.3.1;ICAP Controller;400
8.5.3.3.2;Optimizing Throughput Through Modular Design;402
8.5.3.3.3;Bitstream Verification;403
8.5.4;Results;404
8.5.5;Performance of the Engines;405
8.5.6;Conclusion and Outlook;406
8.5.7;References;407
8.6;Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures;409
8.6.1;Introduction;409
8.6.2;Elliptic Curve Cryptography;410
8.6.2.1;Elliptic Curve Arithmetic;411
8.6.2.2;Finite Field Arithmetic;411
8.6.2.2.1;Karatsuba Multiplication;412
8.6.2.2.2;Multi-Segment-Karatsuba Multiplication;413
8.6.2.2.3;Enhanced Multi-Segment-Karatsuba Multiplication;414
8.6.3;Side Channel Attacks;415
8.6.3.1;Information Leaking of ECC Hardware Architectures;418
8.6.3.2;General Countermeasure Techniques;419
8.6.4;Countermeasure Through Reconfiguration;420
8.6.4.1;Securing ECC on Finite Field Arithmetic Level;421
8.6.4.2;Securing ECC on Elliptic Curve Arithmetic Level;423
8.6.5;DPA Experiments on Countermeasures;425
8.6.5.1;Resistance of the Secured eMSK-Multiplier;426
8.6.6;Conclusion and Future Work;427
8.6.7;References;428
8.7;Reconfigurable Controllers-A Mechatronic Systems Approach;430
8.7.1;Introduction;430
8.7.2;Design Methodology;434
8.7.2.1;Logical Controller Structure and Partitioning;434
8.7.2.2;Specification of Reconfigurable Controller Functionalities;436
8.7.2.3;Distributed Reconfiguration Control and Activation Strategies;437
8.7.3;Structure and Implementation;438
8.7.3.1;Structure and Components;439
8.7.3.2;Implementation and Target Hardware;441
8.7.3.3;Partial Reconfiguration Solution;442
8.7.4;Application;443
8.7.4.1;A Reconfigurable Controller for Piezo-Electric Actuators;443
8.7.5;Conclusion;447
8.7.6;References;448
9;Index;450