Buch, Englisch, 184 Seiten, Previously published in hardcover, Format (B × H): 160 mm x 240 mm, Gewicht: 329 g
Buch, Englisch, 184 Seiten, Previously published in hardcover, Format (B × H): 160 mm x 240 mm, Gewicht: 329 g
Reihe: Frontiers in Electronic Testing
ISBN: 978-1-4419-4052-0
Verlag: Springer US
This book reviews fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs), outlining many methods for designing fault tolerance systems. Some of these are based on new fault-tolerant architecture, and others on protecting the high-level hardware description before synthesis in the FPGA. The text helps the reader choose the best techniques project-by-project, and to compare fault tolerant techniques for programmable logic applications.
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
Radiation Effects in Integrated Circuits.- Single Event Upset (SEU) Mitigation Techniques.- Architectural SEU Mitigation Techniques.- High-Level SEU Mitigation Techniques.- Triple Modular Redundancy (TMR) Robustness.- Designing and Testing a TMR Micro-Controller.- Reducing TMR Overheads: Part I.- Reducing TMR Overheads: Part II.- Final Remarks.
