Rigo / Santos / Azevedo Electronic System Level Design

An Open-Source Approach
1. Auflage 2011
ISBN: 978-1-4020-9940-3
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 146 Seiten

Electronic System Level Design: an Open-Source Approach is based on the successful experience acquired with the conception of the ADL ArchC, the development of its underlying tool suite, and the building of its platform modeling infrastructure. With more than 10000 accesses per year since 2004, the dissemination of ArchC models reached not only students in quest of proper infrastructure to develop their research projects but also some companies in need of processor models to build virtual platforms using SystemC. The need to anticipate the development of hardware-dependent software and to build virtual prototypes gave rise to Transaction Level Modeling (TLM). Since SystemC provided the elements and the adequate abstraction level for supporting TLM, their relation has grown so strong that OSCI created a TLM Working Group whose effort resulted in the recently released TLM 2.0 standard, which is also covered in this book.

Autoren/Hrsg.

Santos, Luiz

Azevedo, Rodolfo

Rigo, Sandro

Inhaltsverzeichnis

1;Preface;5
2;Contents;7
3;Contributors;8
4;Part I: System Design Representation;9
4.1;Chapter 1: Electronic System Level Design;10
4.1.1;1.1 The ESL Concept;10
4.1.2;1.2 Requirements of an ESL Representation;11
4.1.3;1.3 ESL Design Flow;12
4.1.4;1.4 Target Audience, Scope and Organization;15
4.1.5; References;16
4.2;Chapter 2: Open-Source Languages;18
4.2.1;2.1 Basic SystemC Concepts;18
4.2.2;2.2 Introduction to ArchC;23
4.2.2.1;2.2.1 Architecture Resources Description;25
4.2.2.2;2.2.2 Instruction Set Architecture Description;26
4.2.2.2.1;ISA Specification;26
4.2.2.2.2;Instruction Behavior Description;28
4.2.2.3;2.2.3 The Evolution of ArchC Towards Platform Modeling;30
4.2.3; References;31
4.3;Chapter 3: Transaction Level Modeling;32
4.3.1;3.1 Introduction;32
4.3.2;3.2 The Evolution Towards the OSCI TLM 2.0 Standard;34
4.3.3;3.3 Main Features in the TLM 2.0 Standard;35
4.3.4;3.4 A Small TLM Platform Example;38
4.3.5; References;43
5;Part II: Open-Source Models and Tools;44
5.1;Chapter 4: ArchC Model Design Handbook;45
5.1.1;4.1 What Is a Model?;45
5.1.2;4.2 Start Modeling-Architectural Information;46
5.1.3;4.3 Declaring Instructions;49
5.1.4;4.4 Implementing Instructions;53
5.1.5;4.5 Running the Simulator;58
5.1.6;4.6 Debugging the Model-First Steps;60
5.1.6.1;4.6.1 Using the GDB Interface;60
5.1.6.2;4.6.2 Implementing the GDB Interface;61
5.1.7;4.7 Compiler and Operating System Support;69
5.1.7.1;4.7.1 The Helper Methods;70
5.1.7.2;4.7.2 ABI Stub Library;72
5.1.7.3;4.7.3 Startup File;73
5.1.8;4.8 Refining the Model;73
5.1.9;4.9 Going Faster-How to Improve Your Simulator Performance;74
5.1.10; References;75
5.2;Chapter 5: Building Platform Models with SystemC;77
5.2.1;5.1 ArchC and TLM Interface;78
5.2.2;5.2 Platforms with ArchC;80
5.2.3;5.3 Platform Examples;81
5.2.3.1;5.3.1 A Processor-Memory Platform;81
5.2.3.2;5.3.2 Dual Core Platform;84
5.2.4;5.4 The MP3 Example;90
5.2.4.1;5.4.1 Profiling;90
5.2.4.2;5.4.2 Moving the Code to the Platform;93
5.2.4.3;5.4.3 Building the Hardware/Software Interface;93
5.2.4.4;5.4.4 The Next Steps Towards Parallel Software;101
5.3;Chapter 6: Retargetable Binary Tools;105
5.3.1;6.1 Introduction;105
5.3.2;6.2 Language Support for Binary Tools;107
5.3.2.1;6.2.1 Assembly Language Symbols;108
5.3.2.2;6.2.2 Instruction Syntax and Operand Encoding;108
5.3.2.3;6.2.3 Instruction Encoding and Modifiers;109
5.3.2.4;6.2.4 Pseudo Instructions;112
5.3.3;6.3 Binary Tools Retargeting;113
5.3.3.1;6.3.1 GNU Binutils Package;113
5.3.3.2;6.3.2 Automatic Binutils Retargeting;114
5.3.3.3;6.3.3 Opcodes Library Generation;115
5.3.3.4;6.3.4 BFD Library Generation;115
5.3.3.5;6.3.5 Assembler Generation;116
5.3.3.6;6.3.6 Link Editor Generation;116
5.3.3.7;6.3.7 Summary of Generated Files;118
5.3.4;6.4 Putting it to Work;118
5.3.5; References;120
6;Part III: Advanced Topics;121
6.1;Chapter 7: Debugging SystemC Platform Models;122
6.1.1;7.1 Introduction;122
6.1.2;7.2 Model Debugging and Verification in SystemC;123
6.1.3;7.3 Why Computational Reflection?;124
6.1.4;7.4 Enabling Data Introspection in SystemC;125
6.1.5;7.5 Debugging a Platform Simulation Model;127
6.1.6; References;133
6.2;Chapter 8: SystemC-Based Power Evaluation with PowerSC;134
6.2.1;8.1 SystemC Extensions for Power Modeling;134
6.2.1.1;8.1.1 The Extended Design Flow;135
6.2.1.2;8.1.2 The SystemC Extensions;136
6.2.2;8.2 Instrumentation of a SystemC Description;137
6.2.3;8.3 Support for Characterization at the Gate Level;138
6.2.3.1;8.3.1 Integration of Macromodels in PowerSC;139
6.2.4;8.4 Putting PowerSC to Work;145
6.2.4.1;8.4.1 Downloading;145
6.2.4.2;8.4.2 Checking Requirements;146
6.2.4.3;8.4.3 Building the Packages;146
6.2.4.3.1;Building PowerSC;146
6.2.4.3.2;Building PSCLibTools;147
6.2.4.3.3;Building Lib2PSCLib;147
6.2.4.4;8.4.4 Running PowerSC;148
6.2.5; References;149
7;Index;150