Simpson FPGA Design

Best Practices for Team-based Design
1. Auflage 2010
ISBN: 978-1-4419-6339-0
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 151 Seiten

In August of 2006, an engineering VP from one of Altera's customers approached Misha Burich, VP of Engineering at Altera, asking for help in reliably being able to predict the cost, schedule and quality of system designs reliant on FPGA designs. At this time, I was responsible for defining the design flow requirements for the Altera design software and was tasked with investigating this further. As I worked with the customer to understand what worked and what did not work reliably in their FPGA design process, I noted that this problem was not unique to this one customer. The characteristics of the problem are shared by many Corporations that implement designs in FPGAs. The Corporation has many design teams at different locations and the success of the FPGA projects vary between the teams. There is a wide range of design experience across the teams. There is no working process for sharing design blocks between engineering teams. As I analyzed the data that I had received from hundreds of customer visits in the past, I noticed that design reuse among engineering teams was a challenge. I also noticed that many of the design teams at the same Companies and even within the same design team used different design methodologies. Altera had recently solved this problem as part of its own FPGA design software and IP development process.

Phil Simpson is Altera's senior manager for software technical marketing and product planning. In this role, Simpson is responsible for Altera's Quartus II software and third-party EDA interfaces product planning and the creation of the Altera design flow software roadmap. Prior to joining Altera in 1996, Simpson held several engineering roles at various EDA and semiconductor companies, including EDA Solutions, Data I/O and Lucas Aerospace. Simpson holds a BS (with honors) in Electrical & Electronic Engineering from City University, London and an MSC (with distinction) in system design from the University of Central England, Birmingham, England.

Autoren/Hrsg.

Simpson, Philip

Inhaltsverzeichnis

1;Preface;6
2;Contents;8
3;List of Figures;14
4;Chapter 1: Best Practices for Successful FPGA Design;18
4.1;1.1 Introduction;18
5;Chapter 2: Project Management;21
5.1;2.1 The Role of Project Management;21
5.1.1;2.1.1 Project Management Phases;21
5.1.2;2.1.2 Estimating a Project Duration;22
5.1.3;2.1.3 Schedule;22
5.1.3.1;2.1.3.1 Weekly Schedule Analysis;22
5.1.3.2;2.1.3.2 Pro-active Project Management;23
6;Chapter 3: Design Specification;24
6.1;3.1 Design Specification: Communication Is Key to Success;24
6.1.1;3.1.1 High Level Functional Specification;24
6.1.2;3.1.2 Functional Design Specification;25
6.1.2.1;3.1.2.1 Functional Specification Outline;26
6.1.2.2;3.1.2.2 Test Specification Outline;27
7;Chapter 4: Resource Scoping;29
7.1;4.1 Introduction;29
7.2;4.2 Engineering Resources;29
7.3;4.3 Third Party IP;30
7.4;4.4 Device Selection;30
7.4.1;4.4.1 Silicon Specialty Features;31
7.4.2;4.4.2 Density;32
7.4.3;4.4.3 Speed Requirements;33
7.4.4;4.4.4 Pin-Out;33
7.4.5;4.4.5 Power;34
7.4.6;4.4.6 Availability of IP;34
7.4.7;4.4.7 Availability of Silicon;34
7.4.8;4.4.8 Summary;35
8;Chapter 5: Design Environment;36
8.1;5.1 Introduction;36
8.2;5.2 Scripting Environment;36
8.3;5.3 Interaction with Version Control Software;37
8.4;5.4 Use of a Problem Tracking System;38
8.5;5.5 A Regression Test System;39
8.6;5.6 When to Upgrade the Versions of the FPGA Design Tools;39
8.7;5.7 Common Tools in the FPGA Design Environment;40
9;Chapter 6: Board Design;42
9.1;6.1 Challenges that FPGAs Create for Board Design;42
9.2;6.2 Engineering Roles and Responsibilities;43
9.2.1;6.2.1 FPGA Engineers;43
9.2.2;6.2.2 PCB Design Engineer;44
9.2.3;6.2.3 Signal Integrity Engineer;45
9.3;6.3 Power and Thermal Considerations;46
9.3.1;6.3.1 Filtering Power Supply Noise;46
9.3.2;6.3.2 Power Distribution;46
9.4;6.4 Signal Integrity;47
9.4.1;6.4.1 Types of Signal Integrity Problems;47
9.4.1.1;6.4.1.1 Signal Integrity on One Net;47
9.4.1.2;6.4.1.2 Crosstalk;48
9.4.1.3;6.4.1.3 Rail Collapse;48
9.4.2;6.4.2 Electromagnetic Interference;48
9.5;6.5 Design Flows for Creating the FPGA Pinout;49
9.5.1;6.5.1 User Flow 1: FPGA Designer Driven;49
9.5.2;6.5.2 User Flow 2;51
9.5.3;6.5.3 How Do FPGA and Board Engineers Communicate Pin Changes?;53
9.6;6.6 Board Design Check List for a Successful FPGA Pin-Out;53
10;Chapter 7: Power and Thermal Analysis;54
10.1;7.1 Introduction;54
10.2;7.2 Power Basics;55
10.2.1;7.2.1 Static Power;55
10.2.2;7.2.2 Dynamic Power;55
10.2.3;7.2.3 I/O power;55
10.2.4;7.2.4 Inrush Current;56
10.2.5;7.2.5 Configuration Power;56
10.3;7.3 Key Factors in Accurate Power Estimation;56
10.3.1;7.3.1 Accurate Power Models of the FPGA Circuitry;57
10.3.2;7.3.2 Accurate Toggle Rate Data on Each Signal;57
10.3.3;7.3.3 Accurate Operating Conditions;58
10.3.4;7.3.4 Resource Utilization;59
10.4;7.4 Power Estimation Early in the Design Cycle(Power Supply Planning);59
10.5;7.5 Simulation Based Power Estimation(Design Power Verification);60
10.5.1;7.5.1 Partial Simulations;63
10.6;7.6 Best Practices for Power Estimation;63
11;Chapter 8: RTL Design;64
11.1;8.1 Introduction;64
11.2;8.2 Common Terms and Terminology;64
11.3;8.3 Recommendations for Engineers with an ASIC Design Background;66
11.4;8.4 Recommended FPGA Design Guidelines;67
11.4.1;8.4.1 Synchronous Versus Asynchronous;67
11.4.2;8.4.2 Global Signals;67
11.4.2.1;8.4.2.1 Clock Network Resources;68
11.4.3;8.4.3 Dedicated Hardware Blocks;68
11.4.3.1;8.4.3.1 Instantiation Versus Inferencing;69
11.4.4;8.4.4 Use of Low-Level Design Primitives;69
11.4.5;8.4.5 Managing Metastability;70
11.5;8.5 Writing Effective HDL;70
11.5.1;8.5.1 What’s the Best Language;71
11.5.1.1;8.5.1.1 Mixed Language Design;71
11.5.2;8.5.2 Good Design Practices;72
11.5.2.1;8.5.2.1 Documented Code;72
11.5.2.2;8.5.2.2 Recommended Signal Naming Convention;73
11.5.2.3;8.5.2.3 Hierarchy and Design Partitioning;73
11.5.2.4;8.5.2.4 Design Reuse;76
11.5.2.5;8.5.2.5 Techniques for Reducing Design Cycle Time;76
11.5.2.6;8.5.2.6 Design for Debug;77
11.5.3;8.5.3 HDL for Synthesis;78
11.5.3.1;8.5.3.1 Coding Styles;78
11.5.3.2;8.5.3.2 General Verilog Guidelines;79
11.5.3.3;8.5.3.3 General VHDL Guidelines;79
11.5.3.4;8.5.3.4 Designing for Performance;79
11.5.3.4.1;Timing Margin;80
11.5.3.5;8.5.3.5 Designing for Area;81
11.5.3.6;8.5.3.6 Synthesis Tool Settings;81
11.5.3.7;8.5.3.7 Inferencing of FPGA Design Blocks;82
11.5.3.7.1;RAMs;82
11.5.3.7.1.1;Read During Write Behavior;82
11.5.3.7.2;ROMs;83
11.5.3.7.3;Finite State Machines;83
11.5.3.7.3.1;State Machine Encoding Styles;84
11.5.3.7.3.2;Safe State Machines;85
11.5.3.7.3.3;Large Complex State Machines;85
11.5.3.7.4;DSP Blocks;85
11.5.3.7.5;Registers;86
11.5.3.7.5.1;Secondary Signals for Registers;86
11.5.3.7.6;Conditional Statements;87
11.6;8.6 Analyzing the RTL Design;88
11.6.1;8.6.1 Synthesis Reports;88
11.6.1.1;8.6.1.1 Source Files;88
11.6.1.2;8.6.1.2 Synthesis Settings;88
11.6.1.3;8.6.1.3 Resource Usage Information;88
11.6.1.4;8.6.1.4 State Machines;89
11.6.1.5;8.6.1.5 Optimization Information;89
11.6.1.6;8.6.1.6 Timing Estimates;89
11.6.2;8.6.2 Messages;89
11.6.3;8.6.3 Block Diagram View;90
11.7;8.7 Recommended Best Practices for RTL Design;91
12;Chapter 9: IP and Design Reuse;92
12.1;9.1 Introduction;92
12.2;9.2 The Need for IP Reuse;92
12.2.1;9.2.1 Benefits of IP Reuse;93
12.2.2;9.2.2 Challenges in Developing a Design Reuse Methodology;93
12.2.2.1;9.2.2.1 Engineers Mindset;93
12.2.2.2;9.2.2.2 Awareness of Reusable Design Blocks;94
12.2.2.3;9.2.2.3 Development Effort;94
12.3;9.3 Make Versus Buy;95
12.4;9.4 Architecting Reusable IP;96
12.4.1;9.4.1 Specification;96
12.4.2;9.4.2 Implementation Methods;96
12.4.2.1;9.4.2.1 Parameterized RTL;96
12.4.2.2;9.4.2.2 High Level Synthesis;97
12.4.2.3;9.4.2.3 IP Generator;98
12.4.3;9.4.3 Use of Standard Interfaces;98
12.5;9.5 Packaging of IP;99
12.5.1;9.5.1 Documentation;100
12.5.2;9.5.2 User Interface;100
12.5.3;9.5.3 Compatibility with System Integration Tools;101
12.5.4;9.5.4 IP Security;102
12.6;9.6 IP Reuse Checklist;103
13;Chapter 10: The Hardware to Software Interface;104
13.1;10.1 Software Interface;104
13.2;10.2 Definition of Register Address Map;104
13.3;10.3 Use of the Register Address Map;104
13.3.1;10.3.1 IP Selection;105
13.3.2;10.3.2 Software Engineers Interface;105
13.3.3;10.3.3 RTL Engineers Interface;105
13.3.4;10.3.4 Verification Interface;106
13.3.5;10.3.5 Documentation;106
13.4;10.4 Summary;107
14;Chapter 11: Functional Verification;108
14.1;11.1 Introduction;108
14.2;11.2 Challenges of Functional Verification;108
14.3;11.3 Glossary of Verification Concepts;109
14.4;11.4 RTL Versus Gate Level Simulation;110
14.5;11.5 Verification Methodology;110
14.6;11.6 Attack Complexity;111
14.6.1;11.6.1 Modularize Your Design and Your Tests;111
14.6.2;11.6.2 Plan for Expected Operation;111
14.6.3;11.6.3 Plan for the Unexpected;111
14.7;11.7 Functional Coverage;112
14.7.1;11.7.1 Directed Testing;113
14.7.2;11.7.2 Random Dynamic Simulation;113
14.7.3;11.7.3 Constrained Random Tests;113
14.7.4;11.7.4 Use of System Verilog for Design and Verification;113
14.7.4.1;11.7.4.1 Assertions;114
14.7.5;11.7.5 General Testbench Methods;114
14.7.6;11.7.6 Self Verifying Testbenches;115
14.7.7;11.7.7 Formal Equivalency Checking;116
14.8;11.8 Code Coverage;117
14.9;11.9 QA Testing;117
14.9.1;11.9.1 Functional Regression Testing;117
14.9.2;11.9.2 GUI Testing for Reusable IP;118
14.10;11.10 Hardware Interoperability Tests;118
14.11;11.11 Hardware/Software Co-Verification;119
14.11.1;11.11.1 Getting to Silicon Fast;119
14.12;11.12 Functional Verification Checklist;119
15;Chapter 12: Timing Closure;120
15.1;12.1 Timing Closure Challenges;120
15.2;12.2 The Importance of Timing Assignments and Timing Analysis;121
15.2.1;12.2.1 Background;121
15.2.2;12.2.2 Basics of Timing Analysis;122
15.2.2.1;12.2.2.1 Static Timing Analysis;122
15.2.2.2;12.2.2.2 SDC;122
15.2.2.3;12.2.2.3 Clocks;122
15.2.2.4;12.2.2.4 Launch Edge;123
15.2.2.5;12.2.2.5 Latch Edge;123
15.2.2.6;12.2.2.6 Hold Time (th);123
15.2.2.7;12.2.2.7 Set-Up Time (tsu);123
15.2.2.8;12.2.2.8 Arrival Time;124
15.2.2.9;12.2.2.9 Required Time;124
15.2.2.10;12.2.2.10 Slack;125
15.2.2.11;12.2.2.11 Timing Exception;125
15.2.2.12;12.2.2.12 Multi-Cycle Path;125
15.2.2.13;12.2.2.13 False Path;125
15.2.2.14;12.2.2.14 Source Synchronous;126
15.2.2.15;12.2.2.15 Rise/Fall Time;126
15.2.2.16;12.2.2.16 Input Delay;126
15.2.2.17;12.2.2.17 Output Delay;126
15.2.2.18;12.2.2.18 Operating Conditions;127
15.2.2.19;12.2.2.19 Multi-corner Analysis;127
15.2.2.20;12.2.2.20 Slow Corner Model;127
15.2.2.21;12.2.2.21 Fast Corner Model;127
15.2.2.22;12.2.2.22 Clock Uncertainty;127
15.2.2.23;12.2.2.23 Clock Latency;128
15.3;12.3 A Methodology for Successful Timing Closure;128
15.3.1;12.3.1 Family and Device Assignments;128
15.3.1.1;12.3.1.1 Speed-Grade Selection;128
15.3.1.2;12.3.1.2 I/O Settings;129
15.3.2;12.3.2 Design Planning;129
15.3.2.1;12.3.2.1 Incremental Compilation;130
15.3.2.1.1;Top-Down Design Flow;131
15.3.2.1.2;Bottom-Up Design Flow;131
15.3.2.2;12.3.2.2 Design Scenarios Using Incremental Compilation;132
15.3.2.2.1;Scenario 1: Parameter Tuning;133
15.3.2.2.2;Scenario 2: Bug Fixing;133
15.3.2.2.3;Scenario 3: Timing Closure;134
15.3.3;12.3.3 Early Timing Estimation;134
15.3.4;12.3.4 CAD Tool Settings;135
15.3.4.1;12.3.4.1 Understanding the Fitter (Place and Route);135
15.3.4.2;12.3.4.2 Advanced Optimization: When You Need More;136
15.3.4.2.1;Physical Synthesis Optimizations;136
15.3.4.2.2;Design Space Exploration;137
15.3.4.3;12.3.4.3 Compilation Reports and Analysis Tools;137
15.3.4.4;12.3.4.4 Floorplanning Tools;139
15.3.4.4.1;Architecture Exploration;141
15.3.4.4.2;Analysis of Placement and Routing;141
15.3.4.4.3;Floorplan Assignments;141
15.3.4.4.4;Engineering Change Orders;142
15.4;12.4 Common Timing Closure Issues;142
15.4.1;12.4.1 Missing Timing Constraints;143
15.4.2;12.4.2 Conflicting Timing Constraints;143
15.4.3;12.4.3 High Fan-Out Registers;143
15.4.4;12.4.4 Missing Timing by a Small Margin;144
15.4.5;12.4.5 Restrictive Location Constraints;144
15.4.6;12.4.6 Long Compile Times;144
15.5;12.5 Design Planning, Implementation, Optimizationand Timing Closure Checklist;145
16;Chapter 13: In-System Debug;146
16.1;13.1 In-System Debug Challenges;146
16.2;13.2 Planning;147
16.3;13.3 Techniques;147
16.3.1;13.3.1 Use of Pins for Debug;147
16.3.2;13.3.2 Internal Logic Analyzer;148
16.3.2.1;13.3.2.1 The Design Flow with an ILA;150
16.3.2.2;13.3.2.2 ILA Limitations;150
16.3.2.3;13.3.2.3 Tips;150
16.3.2.3.1;Remote Debug;150
16.3.2.3.2;Interface to MATLAB;151
16.3.2.3.3;Insufficient Device Resources;151
16.3.3;13.3.3 Use of Debug Logic;151
16.3.4;13.3.4 External Logic Analyzer;152
16.3.5;13.3.5 Editing Memory Contents;152
16.3.6;13.3.6 Use of a Soft Processor for Debug;153
16.4;13.4 Use Scenarios;153
16.4.1;13.4.1 Power-Up Debug;153
16.4.2;13.4.2 Debug of Transceiver Interfaces;154
16.4.3;13.4.3 Reporting of System Performance;154
16.4.4;13.4.4 Debug of Soft Processors;155
16.4.4.1;13.4.4.1 Software Profiling;155
16.4.4.2;13.4.4.2 Watchpoints;156
16.4.4.3;13.4.4.3 Stack Overflow;156
16.4.4.4;13.4.4.4 Breakpoints;156
16.4.4.5;13.4.4.5 Step Through the Code;156
16.4.5;13.4.5 Device Programming Issues;156
16.5;13.5 In-System Debug Checklist;157
17;Chapter 14: Design Sign-Off;158
17.1;14.1 Sign-Off Process;158
17.2;14.2 After Sign-Off;158
18;Bibliography;160
19;Index;161