Buch, Englisch, Band 3164, 215 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 359 g
Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers
Buch, Englisch, Band 3164, 215 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 359 g
Reihe: Lecture Notes in Computer Science
ISBN: 978-3-540-24031-0
Verlag: Springer Berlin Heidelberg
This book collects the thoroughly refereed post-proceedings of the Third International Workshop on Power-Aware Computer Systems, PACS 2003, held in San Diego, CA, USA in December 2003. The 14 revised full papers presented were carefully selected during two rounds of reviewing and improvement from 43 submissions. The papers span a wide spectrum of topics in power-aware systems; they are organized in topical sections on compilers, embedded systems, microarchitectures, and cache and memory systems.
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
- Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur
- Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
- Mathematik | Informatik EDV | Informatik Technische Informatik Hochleistungsrechnen, Supercomputer
- Mathematik | Informatik EDV | Informatik Technische Informatik Hardware: Grundlagen und Allgemeines
Weitere Infos & Material
Compilers.- Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency.- Inter-program Compilation for Disk Energy Reduction.- Embedded Systems.- Energy Consumption in Mobile Devices: Why Future Systems Need Requirements–Aware Energy Scale-Down.- Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems.- Online Prediction of Battery Lifetime for Embedded and Mobile Devices.- Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.- Heterogeneous Wireless Network Management.- Microarchitectural Techniques.- “Look It Up” or “Do the Math”: An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization.- CPU Packing for Multiprocessor Power Reduction.- Exploring the Potential of Architecture-Level Power Optimizations.- Coupled Power and Thermal Simulation with Active Cooling.- Cache and Memory Systems.- The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling.- Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.- PARROT: Power Awareness Through Selective Dynamically Optimized Traces.
