Buch, Englisch, 1168 Seiten, Format (B × H): 175 mm x 250 mm, Gewicht: 1783 g
ISBN: 978-1-119-96517-6
Verlag: Wiley
The ESD Handbook offers a comprehensive reference that explores topics relevant to ESD design in semiconductor components and explores ESD in various systems. Electrostatic discharge is a common problem in the semiconductor environment and this reference fills a gap in the literature by discussing ESD protection. Written by a noted expert on the topic, the text offers a topic-by-topic reference that includes illustrative figures, discussions, and drawings.
The handbook covers a wide-range of topics including ESD in manufacturing (garments, wrist straps, and shoes); ESD Testing; ESD device physics; ESD semiconductor process effects; ESD failure mechanisms; ESD circuits in different technologies (CMOS, Bipolar, etc.); ESD circuit types (Pin, Power, Pin-to-Pin, etc.); and much more. In addition, the text includes a glossary, index, tables, illustrations, and a variety of case studies.
* Contains a well-organized reference that provides a quick review on a range of ESD topics
* Fills the gap in the current literature by providing information from purely scientific and physical aspects to practical applications
* Offers information in clear and accessible terms
* Written by the accomplished author of the popular ESD book series
Written for technicians, operators, engineers, circuit designers, and failure analysis engineers, The ESD Handbook contains an accessible reference to ESD design and ESD systems.
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
About the Author xxxvii
Acknowledgements xxxix
1 ESD, EOS, EMI, EMC, and Latchup 1
1.1 Electrostatic Discharge (ESD) 1
1.2 Human Body Model (HBM) 2
1.3 Machine Model (MM) 3
1.4 Cassette Model 3
1.5 Charged Device Model (CDM) 4
1.6 Transmission Line Pulse (TLP) 5
1.7 Very Fast Transmission Line Pulse (VF-TLP) 8
1.8 Electrical Overstress (EOS) 8
1.9 Electrical Overstress (EOS) 8
1.10 EOS Sources - Lightning 9
1.11 EOS Sources - Electromagnetic Pulse (EMP) 9
1.12 EOS Sources - Machinery 10
1.13 EOS Sources - Power Distribution 10
1.14 EOS Sources - Switches, Relays, and Coils 10
1.15 EOS Design Flow and Product Definition 10
1.16 EOS Sources - Design Issues 11
1.17 Electromagnetic Interference (EMI) 12
1.18 Electromagnetic Compatibility (EMC) 13
1.19 Latchup 13
Questions and Answers 14
1.20 Summary and Closing Comments 15
References 15
2 ESD in Manufacturing 21
2.1 Flooring 21
2.2 Work Surfaces 21
2.3 Garments 22
2.4 Wrist Straps 22
2.5 Shoes - Footwear 22
2.6 Ionization 23
2.7 Clean Rooms 24
2.8 Carts 26
2.9 Shipping Tubes 26
2.10 Trays 27
2.11 Measurements 27
2.12 Verification 28
2.13 Audit 28
2.14 Triboelectric Charging - How Does it Happen? 29
2.15 Conductors, Semiconductors, and Insulators 30
2.16 Static Dissipative Materials 30
2.17 ESD and Materials 31
2.18 Electrification and Coulomb's Law 31
2.19 Electromagnetism and Electrodynamics 33
2.20 Electrical Breakdown 33
2.21 Electro-Quasistatics and Magnetoquasistatics 36
2.22 Electrodynamics and Maxwell's Equations 36
2.23 Electrostatic Discharge (ESD) 36
2.24 Electromagnetic Compatibility (EMC) 37
2.25 Electromagnetic Interference (EMI) 37
2.26 Fundamentals of Manufacturing and Electrostatics 37
2.27 Materials, Tooling, Human Factors, and Electrostatic Discharge 38
2.28 Materials and Human-induced Electric Fields 39
2.29 Manufacturing Environment and Tooling 39
2.30 Manufacturing Equipment and ESD Manufacturing Problems 39
2.31 Manufacturing Materials 39
2.32 Measurement and Test Equipment 40
2.33 Manufacturing Testing for Compliance 41
2.34 Grounding and Bonding Systems 42
2.35 Work Surfaces 42
2.36 Wrist Straps 43
2.37 Constant Monitors 43
2.38 Footwear 43
2.39 Floors 44
2.40 Personnel Grounding with Garments 44
2.41 Garments 44
2.42 Air Ionization 44
2.43 Seating 45
2.44 Packaging and Shipping 46
2.45 Trays 46
2.46 ESD Identification 46
2.47 ESD Program Auditing 46
2.48 ESD On-Chip Protection 47
2.49 ESD, EOS, EMI, EMC, and Latchup 47
2.50 Manufacturing Electrical Overstress (EOS) 48
2.51 EMI 50
2.52 EMC 50
2.53 Summary and Closing Comments 50
References 50
3 ESD Standards 55
3.1 Factory - Flooring 55
3.2 Factory - Resistance Measurement of Materials 56
3.3 JEDEC 58
3.4 International Electro-Technical Commission (IEC) 59
3.5 IEEE 59
3.6 Department of Defense (DOD) 59
3.7 Military Standards 59
3.8 SAE 60
3.9 Summary and Closing Comments 60
Questions and Answers 60
References 61
4 ESD Testing 65
4.1 Electrostatic Discharge (ESD) Testing 65
4.2 ESD Models 65
4.3 HBM Test System 69
4.4 HBM Two-pin Test System 69
4.5 Machine Model (MM) 69
4.6 Small Charge Model (SCM) 70
4.7 Small Charge Model Source 71
4.8 CDM Pulse Waveform 72
4.9 HMM Equivalent Circuit 77
4.10 HMM Test Equipment 77
4.11 HMM Test Configuration 78
4.12 HMM Fixture Board 78
4.13 Transmission Line Pulse (TLP) 82
4.14 TLP Test Systems 84
4.15 IEC 61000-4-2 87
4.16 Equivalent Circuit 89
4.17 Test Equipment 89
4.18 Cable Discharge Event (CDE) 90
4.19 CDE Pulse Waveform 93
4.20 Equivalent Circuit 93
4.21 Commercial Test Systems 94
4.22 Systems Electromagnetic Interference (EMI) 95
4.23 Electromagnetic Compatibility (EMC) 95
4.24 Electrical Overstress (EOS) 95
4.25 Latchup 95
4.26 Electrical Overstress (EOS) 95
4.27 EOS Sources - Lightning 96
4.28 EOS Sources - Electromagnetic Pulse (EMP) 97
4.29 Electromagnetic Compatibility 97
4.30 Summary and Closing Comments 100
References 100
5 ESD Device Physics 117
5.1 Electro-thermal Instability 117
5.2 Stable System 118
5.3 Unstable System 118
5.4 Differential Relation of Voltage and Current 120
5.5 Time Constant Hierarchy 121
5.6 Thermal Physics Time Constants 121
5.7 Adiabatic, Thermal Diffusion Time Scale and Steady State 121
5.8 Electro-quasistatic and Magnetoquasistatics 122
5.9 Electrical Instability 124
5.10 Thermal Physics Time Constants 125
5.11 Adiabatic, Thermal Diffusion Time Scale and Steady State 126
5.12 Electrical Instability and Breakdown 126
5.13 Spatial Instability and Electro-thermal Current Constriction 127
5.14 Equipotential Surface 127
5.15 Heat Flow 128
5.16 Conservation of Heat 128
5.17 Electric Potential and Temperature Gradient 128
5.18 Electric Energy, Resistivity, and Thermal Conductivity 129
5.19 Breakdown 131
5.20 Electron Current Continuity Relationship 136
5.21 Air Breakdown and Peak Currents 138
5.22 Electro-thermal Instability 139
5.23 Mathematical Methods - Green's Function and Method of Images 141
5.24 Mathematical Methods - Green's Function and Method of Images 143
5.25 Mathematical Methods - Integral Transforms of the Heat Conduction Equation 148
5.26 Flux Potential Transfer Relations Matrix Methodology 152
5.27 Heat Equation Variable Conductivity 154
5.28 Mathematical Methods - Boltzmann Transformation 156
5.29 Mathematical Methods - The Duhamel Formulation 158
5.30 Spherical Source Tasca Model 160
5.31 Wunsch-Bell Model 163
5.32 The Smith and Littau Model 166
5.33 The Arkihpov-Astvatsaturyan-Godovosyn-Rudenko Model 168
5.34 The Vlasov-Sinkevitch Model 169
5.35 The Dwyer, Franklin and Campbell Model 169
5.36 Negative Differential Resistor and Resistor Ballasting 174
5.37 Ash Model - Nonlinear Failure Power Thresholds 176
5.38 Statistical Models for ESD Prediction 178
5.39 Summary and Closing Comments 180
References 180
6 ESD Events and Protection Circuits 189
6.1 Human Body Model (HBM) 189
6.2 Machine Model (MM) 191
6.3 Charged Device Model 193
6.4 Human Metal Model (HMM) 197
6.5 IEC 61000-4-2 History 204
6.6 IEC 61000-4-5 209
6.7 Cable Discharge Event (CDE) 213
6.8 CDM Scope 215
References 219
7 ESD Failure Mechanism 235
7.1 Tables of CMOS ESD Failure Mechanisms 235
7.2 LOCOS Isolation-Defined CMOS 235
7.3 LOCOS-bound Thick Oxide MOSFET 241
7.4 LOCOS-Bound Structures 242
7.5 Shallow Trench Isolation (STI) 245
7.6 STI Pull-down ESD Failure Mechanism 245
7.7 STI Pull-Down and Gate Wrap-Around 246
7.8 MOSFETs 247
7.9 LOCOS-bound Thick Oxide MOSFET 252
7.10 Bipolar Transistor Devices 254
7.11 Silicide Blocked N-diffusion Resistors 259
7.12 Silicon Germanium ESD Failure Mechanisms 259
7.13 Silicon Germanium Carbon ESD Failure Mechanisms 259
7.14 Gallium Arsenide Technology ESD Failure Mechanisms 260
7.15 Indium Gallium Arsenide ESD Failure Mechanisms 261
7.16 Micro Electromechanical (MEM) Systems 263
7.17 Micro-mirror Array Failures 265
7.18 EOS Bond Pad and Interconnect Failure 269
7.19 Summary and Closing Comments 272
References 273
8 ESD Design Synthesis 281
8.1 ESD Design Synthesis and Architecture Flow 281
8.2 ESD Design - the Signal Path and the Alternate Current Path 287
8.3 ESD Electrical Circuit and Schematic Architecture Concepts 289
8.4 The Ideal ESD Network 289
8.5 Mapping Semiconductor Chips and ESD Designs 293
8.6 Mapping across Semiconductor Fabricators 294
8.7 ESD Design Mapping across Technology Generations 295
8.8 ESD Networks, Sequencing, and Chip Architecture 306
8.9 ESD Layout and Floorplan-related Concepts 314
8.10 ESD Architecture and Floor-planning 323
8.11 Digital and Analog CMOS Architecture 347
8.12 Digital and Analog Floorplan - Placement of Analog Circuits 348
8.13 Mixed-signal Architecture - Digital, Analog, and RF Architecture 350
8.14 Summary and Closing Comments 351
Questions 351
References 352
9 On-chip ESD Protection Circuits - Input Circuitry 363
9.1 Receivers and ESD 363
9.2 Receivers and Receiver Delay Time 363
9.3 ESD Loading Effect on Receiver Performance 364
9.4 Receivers and HBM 365
9.5 Receivers and CDM 366
9.6 Receivers and Receiver Evolution 368
9.7 Receiver Circuits with Half-pass Transmission Gate 368
9.8 Receiver with Full-pass Transmission Gate 371
9.9 Receiver, Half-pass Transmission Gate, and Keeper Network 373
9.10 Receiver, Half-pass Transmission Gate, and the Modified Keeper Network 377
9.11 Receiver Circuits with Pseudo-zero VT Half-pass Transmission Gates 379
9.12 Receiver with Zero VT Transmission Gate 381
9.13 Receiver Circuits with Bleed Transistors 383
9.14 Receiver Circuits with Test Functions 384
9.15 Receiver with Schmitt Trigger Feedback Network 385
9.16 Bipolar Transistor Receivers 389
9.17 CMOS Differential Receiver with Analog Layout Concepts 397
9.18 CMOS Differential Receiver Capacitance Loading 398
9.19 CMOS Differential Receiver ESD Mismatch 398
9.20 Analog Differential Pair ESD Signal Pin Matching with CommonWell Layout 400
9.21 Analog Differential Pair Common Centroid Design Layout - Signal-Pin to Signal-Pin and Parasitic ESD Elements 403
9.22 Off-chip Drivers (OCD) 405
9.23 Off-chip Driver I/O Standards and ESD 407
9.24 Off-chip Driver (OCD) ESD Design Basics 408
9.25 Off-chip Drivers (OCD): Mixed Voltage Interface 414
9.26 Off-chip Drivers (OCD): Self-bias Well OCD Networks 414
9.27 Self-bias Well Off-chip Driver (OCD) Networks 415
9.28 ESD Protection Networks for Self-bias Well OCD Networks 417
9.29 Programmable Impedance Off-chip Driver (OCD) Network 418
9.30 ESD Input Protection Networks for Programmable Impedance Off-chip Drivers 422
9.31 Universal Off-chip Drivers 423
9.32 Gate Array Off-chip Driver Design 423
9.33 Gate Array OCD Design - Impedance Matching of Unused Elements 425
9.34 OCD ESD Design - Power Rails Over Multi-finger MOSFETs 426
9.35 Off-chip Driver: Gate-modulated MOSFET ESD Network 427
9.36 Off-chip Driver Simplified Gate Modulated Network 428
9.37 Off-chip Drivers ESD Design: Integration of Coupling and Ballasting Techniques 428
9.38 Ballasting and Coupling 429
9.39 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with Diode 429
9.40 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with a MOSFET 430
9.41 Gate-coupled Domino Resistor-ballasted MOSFET 431
9.42 Substrate-modulated Resistor Ballasted MOSFET 433
9.43 Summary and Closing Comments 434
Problems 435
References 437
10 On-Chip ESD Protection Circuits - ESD Power Clamps 441
10.1 ESD Power Clamps 441
10.2 ESD Power Clamp Design Practices 441
10.3 Current Loops 442
10.4 Impedance 442
10.5 Segmentation 443
10.6 Voltage Limitations 443
10.7 Latchup 443
10.8 ESD Power Clamp Circuits 444
10.9 Classification of ESD Power Clamps 444
10.10 Master-Slave ESD Power Clamps 445
10.11 Trigger Networks 445
10.12 ESD Power Clamp Characteristics and Issues 445
10.13 Design Synthesis of ESD Power Clamp - Key Design Parameters 446
10.14 Design Synthesis of ESD Power Clamps Trigger Networks 446
10.15 Transient Response Frequency Trigger Element and the ESD Frequency Window 446
10.16 ESD Power Clamp Frequency Design Window 447
10.17 Design Synthesis of ESD Power Clamp - Voltage Triggered ESD Trigger Elements 448
10.18 Design Synthesis of ESD Power Clamp - The ESD Power Clamp Shunting Element 449
10.19 ESD Power Clamp Trigger Condition vs. Shunt Failure 450
10.20 ESD Clamp Element - Width Scaling 450
10.21 ESD Clamp Element - On-resistance 450
10.22 ESD Clamp Element - Safe Operating Area (SOA) 451
10.23 ESD Power Clamp Issues 451
10.24 ESD Power Clamp Issues - Power-up and Power-down 451
10.25 ESD Power Clamp Issues - False Triggering 452
10.26 ESD Power Clamp Issues - Pre-charging 452
10.27 ESD Power Clamp Issues - Post-charging 452
10.28 ESD Power Clamp Design 453
10.29 ESD Power Clamp Design Synthesis - Forward Bias Triggered ESD Power Clamps 456
10.30 Series Stacked RC-triggered ESD Power Clamps 459
10.31 Triple Well Diode String ESD Power Clamp 463
10.32 Bipolar ESD Power Clamps 464
10.33 ESD Power Clamp Design Synthesis - Bipolar ESD Power Clamps 469
10.34 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance-triggered 480
10.35 Silicon Controlled Rectifier Power Clamps 481
References 486
11 ESD Architecture and Floor Planning 491
11.1 ESD Design Floor Plan 491
11.2 Peripheral I/O Design 492
11.3 Pad Limited Peripheral I/O Design Architecture 493
11.4 Pad Limited Peripheral I/O Design Architecture - Staggered I/O 493
11.5 Core Limited Peripheral I/O Design Architecture 495
11.6 Lumped ESD Power Clamp in Peripheral I/O Design Architecture 496
11.7 Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners 496
11.8 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Power Pads 497
11.9 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Master/Slave ESD Power Clamp System 498
11.10 Array I/O 498
11.11 Array I/O Nibble Architecture 501
11.12 Array I/O Pair Architecture 503
11.13 Array I/O - Fully Distributed 504
11.14 ESD Architecture - Dummy Bus Architecture 507
11.15 ESD Architecture - Dummy VDD Bus 507
11.16 ESD Architecture - Dummy Ground (VSS) Bus 508
11.17 Native Voltage Power Supply Architecture 508
11.18 Single Power Supply Architecture 509
11.19 Mixed Voltage Architecture 509
11.20 Mixed Voltage Architecture - Single Power Supply 509
11.21 Mixed Voltage Architecture - Dual Power Supply 511
11.22 Mixed Signal Architecture 514
11.23 Digital and Analog Floor Plan - Placement of Analog Circuits 515
11.24 Mixed Signal Architecture - Digital, Analog, and RF Architecture 518
11.25 ESD Power Grid Design 519
11.26 I/O to Core Guard Rings 525
11.27 Within I/O Guard Rings 527
11.28 ESD-to-I/O Off-Chip Driver (OCD) Guard Ring 527
11.29 Guard Rings and Computer Aided Design (CAD) Methods 539
11.30 Summary and Closing Comments 541
References 541
12 ESD Digital Design 551
12.1 Fundamental Concepts of ESD Design 551
12.2 Concepts of ESD Digital Design 551
12.3 Device Response to External Events 552
12.4 Alternative Current Loops 553
12.5 Decoupling of Feedback Loops 554
12.6 Decoupling of Power Rails 554
12.7 Local and Global Distribution 554
12.8 Usage of Parasitic Elements 555
12.9 Unused Section of a Semiconductor Device, Circuit, or Chip Function 556
12.10 Unused Corners 556
12.11 Unused White Space 556
12.12 Impedance Matching Between Floating and Non-floating Networks 556
12.13 Unconnected Structures 557
12.14 Symmetry 557
12.15 Design Synthesis 557
12.16 ESD, Latchup, and Noise 559
12.17 Structures Under Bond Pads 574
12.18 Summary and Closing Comments 575
References 576
13 ESD Analog Design 583
13.1 Analog Design: Local Matching 583
13.2 Analog Design: Global Matching 583
13.3 Symmetry 584
13.4 Analog Design - Local Matching 584
13.5 Analog Design - Global Matching 584
13.6 Common Centroid Design 586
13.7 Common Centroid Arrays 586
13.8 Interdigitation Design 586
13.9 Common Centroid and Interdigitation Design 587
13.10 Dummy Resistor Layout 593
13.11 Thermoelectric Cancelation Layout 593
13.12 Electrostatic Shield 593
13.13 Interdigitated Resistors and ESD Parasitics 594
13.14 Capacitor Element Design 595
13.15 Inductor Element Design 596
13.16 ESD Failure in Inductors 597
13.17 Inductor Physical Variables 598
13.18 Inductor Element Design 599
13.19 Diode Design 599
13.20 Analog ESD Circuits 602
13.21 ESD MOSFETs 607
13.24 Analog Differential Pair Common Centroid Design Layout - Signal-pin to Signal-pin and Parasitic ESD Elements 620
13.25 Summary and Closing Comments 624
References 624
14 ESD RF Design 629
14.1 Fundamental Concepts of ESD Design 629
14.2 Fundamental Concepts of RF ESD Design 632
14.3 RF CMOS Input Circuits 637
14.4 RF CMOS Impedance Isolation LC Resonator ESD Networks 647
14.5 RF CMOS LC-diode Networks Experimental Results 648
14.6 RF CMOS LNA ESD Design - Low Resistance ESD Inductor and ESD Diode Clamping Elements in Pi-configuration 650
14.7 RF CMOS T-coil Inductor ESD Input Network 653
14.8 RF CMOS Distributed ESD Networks 655
14.9 RF CMOS Distributed ESD-RF Networks 656
14.10 RF CMOS Distributed RF-ESD Networks Using Series Inductors and Dual-diode Shunts 656
14.11 RF CMOS Distributed RF-ESD Networks Using Series Inductors and MOSFET Parallel Shunts 659
14.12 RF CMOS Distributed ESD Networks - Transmission Lines and Co-planar Waveguides 661
14.13 RF CMOS - ESD and RF LDMOS Power Technology 663
14.14 Summary and Closing Comments 666
References 666
15 ESD Power Electronics Design 681
15.1 Reliability Technology Scaling and the Reliability Bathtub Curve 681
15.2 Input Circuitry 686
15.3 Summary and Closing Comments 702
References 702
16 ESD in Advanced CMOS 709
16.1 Interconnects and ESD 709
16.2 Aluminum Interconnects 710
16.3 Interconnects - Vias 714
16.4 Interconnects - Wiring 715
16.5 Junctions 719
16.6 Titanium Silicide 725
16.7 Shallow Trench Isolation 731
16.8 LOCOS-bound ESD Structures 734
16.9 LOCOS-bound p+/n-well Junction Diodes 734
16.10 LOCOS-bound n+ Junction Diodes 736
16.11 LOCOS-bound n-well/Substrate Diodes 737
16.12 LOCOS-bound Lateral N-Well to N-Well Bipolar ESD Element 738
16.13 LOCOS-bound Lateral N+ to N-well Bipolar ESD Element 738
16.14 LOCOS-bound Lateral pnp Bipolar ESD Element 739
16.15 LOCOS-bound Thick Oxide MOSFET ESD Element 739
16.16 Shallow Trench Isolation 739
16.17 STI-bound ESD Structures 741
16.18 Substrate Modeling - Electrical and Thermal Discretization 746
16.19 Heavily Doped Substrates 750
16.20 Retrograde Wells and ESD Scaling 766
16.21 Triple Well and Isolated MOSFET CMOS 775
16.22 Summary and Closing Comments 779
References 779
17 ESD in Silicon on Insulator 783
17.1 Silicon on Insulator (SOI) Technologies 783
17.2 Elimination of CMOS Latchup 784
17.3 Lack of Vertical Bipolar Transistors 785
17.4 Floating Gate Tie Downs 785
17.5 Physical Separation of MOSFETs from the Bulk Substrate 785
17.6 SOI ESD Design Fundamental Concepts 786
17.7 SOI Lateral Diode Structure 791
17.8 Transistors - Bulk versus SOI Technology 791
17.9 SOI Buried Resistors (BR) Elements 796
17.10 Dynamic Threshold MOS (DTMOS) SOI MOSFET 797
17.11 SOI P+ Body Contact Abutting n+ Drain 798
17.12 Transmission Line Pulse (TLP) Testing of SOI Diode Designs 798
17.13 SOI ESD with MOSFET Drain and Body Width Ratio Variation 799
17.14 SOI Dual-Gate MOSFET Structure 799
17.15 SOI ESD Design - Mixed Voltage T-Shape Layout Style 800
17.16 SOI ESD Design: Double Diode Network 802
17.17 Bulk to SOI ESD Design Remapping 803
17.18 SOI ESD Diode Design Parameters 804
17.19 SOI ESD Design in Mixed Voltage Interface Environments 808
17.20 Comparison of Bulk with SOI ESD Results 809
17.21 SOI ESD Design with Aluminum Interconnects 810
17.22 SOI ESD Design with Copper Interconnects 812
17.23 SOI ESD Design with Gate Circuitry 813
17.24 Summary and Closing Comments 815
References 815
18 ESD in Analog Circuits 821
18.1 Analog Design Circuits 821
18.2 Single-ended Receivers 822
18.3 Schmitt Trigger Receivers 822
18.4 Differential Receivers 822
18.5 Comparators 824
18.6 Current Sources 825
18.7 Current Mirrors 825
18.8 Widlar Current Mirror 826
18.9 Wilson Current Mirror 826
18.10 Voltage Regulators 827
18.11 Buck Converters 828
18.12 Boost Converters 828
18.13 Buck-Boost Converters 829
18.14 Cuk Converters 830
18.15 Voltage Reference Circuits 830
18.16 Brokaw Bandgap Voltage Reference 830
18.17 Converters 831
18.18 Analog-to-Digital Converter (ADC) 831
18.19 Digital-to-Analog Converters (DAC) 832
18.20 Oscillators 832
18.21 Phase Lock Loop (PLL) Circuits 832
18.22 Delay Locked Loop (DLL) 833
18.23 Analog and ESD Design Synthesis 833
18.24 Analog Chip Architecture - Separation of Analog Power from Digital Power, AVDD-DVDD 836
18.25 ESD Failure in Phase Lock Loop (PLL) and System Clock 837
18.26 ESD Failure in Current Mirrors 837
18.27 ESD Failure in Schmitt Trigger Receivers 838
18.28 ESD Design Practice - Prevent ESD Failure in Schmitt Trigger 840
18.29 Analog-Digital Architecture: Isolated Digital and Analog Domains 841
18.30 ESD Protection Solution - Connectivity of AVDD-to-VDD 842
18.31 ESD Solution: Connectivity of AVSS-to-DVSS 843
18.32 Digital and Analog Domain with ESD Power Clamps 843
18.33 Digital and Analog Domain with Master-Slave ESD Power Clamps 846
18.34 High Voltage, Digital, and Analog Domain Floorplan 846
18.35 Floor-planning of Digital and Analog 846
18.36 Inter-domain Signal Lines ESD Failures 849
18.37 Digital-to-Analog Signal Line ESD Failures 849
18.38 Digital-to-Analog Core Spatial Isolation 851
18.39 Digital-to-Analog Core Ground Coupling 851
18.40 Digital-to-Analog Core Resistive Ground Coupling 852
18.41 Digital-to-Analog Core Diode Ground Coupling 852
18.42 Domain-to-Domain Signal Line ESD Networks 852
18.43 Domain-to-Domain Third-party Coupling Networks 853
18.44 Domain-to-Domain Cross-domain ESD Power Clamp 854
18.45 Digital-to-Analog Domain Moat 855
18.46 Analog and ESD Circuit Integration 855
18.47 Integrated Body Ties 856
18.48 Self-Protecting vs Non-self Protecting Designs 856
References 856
19 ESD in RF CMOS 865
19.1 CMOS and ESD 865
19.2 RF CMOS 865
19.3 RF CMOS and ESD 865
19.4 RF CMOS ESD Failure Mechanisms 865
19.5 RF CMOS - ESD Device Comparisons 866
19.6 RF ESD Metrics 867
19.7 Grounded Gate n-channel MOSFET versus STI Diode 868
19.8 Silicon-controlled Rectifier 869
19.9 SCR versus GGNMOS 869
19.10 Shallow Trench Isolation and Polysilicon Gated Diodes 869
19.11 RF ESD Design 870
19.12 RF ESD Design Layout - Circular RF ESD Devices 870
19.13 Disadvantage of RF ESD Circular Element 871
19.14 RF ESD Design - ESD Wiring Design 872
19.15 RF ESD Design - Loading Capacitance 872
19.16 Metal Capacitance 873
19.17 Analog Metal (AM) 873
19.18 RF ESD Design Practices 874
19.19 RF Passives - ESD and Schottky Barrier Diodes 874
19.20 Schottky Barrier Diodes and Metallurgy 875
19.21 Silicon Germanium Schottky Barrier Diodes 876
19.22 Schottky Barrier RF ESD Design Practice 877
19.23 RF Passives - ESD and Inductors 877
19.24 Quality Factor, Q 878
19.25 Incremental Model of an Inductor 878
19.26 Inductor Coil Parameters 878
19.27 RF Passives - ESD and Capacitors 882
19.28 Capacitors and RF Applications 882
19.29 Capacitors in ESD Networks 882
19.30 Types of Radio Frequency Capacitors 883
19.31 Metal-Oxide-Semiconductor and Metal-Insulator-Metal Capacitors 883
19.32 Varactors and Hyper-abrupt Junction Varactor Capacitors 884
19.33 Metal-ILD-Metal Capacitors 884
19.34 Vertical Parallel Plate (VPP) Capacitors 884
19.35 Tips: ESD RF Design Practices for Capacitors 885
19.36 Summary and Closing Comments 886
Problems 886
References 888
20 ESD in Silicon Germanium 891
20.1 Heterojunctions Bipolar Transistors 891
20.2 Silicon Germanium 891
20.3 Silicon Germanium HBT Devices 892
20.4 Silicon Germanium Device Structure 893
20.5 Silicon Germanium Film Deposition 894
20.6 Silicon Germanium Emitter-Base Region 895
20.7 Silicon Germanium Physics 895
20.8 Silicon Germanium Bandgap 896
20.9 Silicon Germanium Intrinsic Temperature 896
20.10 Position-dependent Silicon Germanium Profile 896
20.11 Position-dependent Intrinsic Temperature 897
20.12 SiGe Collector Current with Graded Germanium Concentration 897
20.13 Silicon Germanium ESD and Time Constants 898
20.14 Silicon Germanium Base Transit Time 898
20.15 Silicon Germanium Breakdown Voltages 898
20.16 Silicon Germanium ESD Measurements 899
20.17 Silicon Germanium Collector-to-Emitter ESD Stress 899
20.18 Transmission Line Pulse Testing of Silicon Germanium HBT 899
20.19 Transmission Line Pulse (TLP) I-V Characteristic 899
20.20 Wunsch-Bell Characteristic of Silicon Germanium HBT 901
20.21 Comparison of Silicon Germanium HBT and Silicon BJT 901
20.22 Wunsch-Bell Characteristic of SiGe HBT versus Si BJT 902
20.23 Intrinsic Base Resistance in SiGe HBT 904
20.24 SiGe HBT Electro-thermal HBM Simulation of Collector-Emitter Stress 904
20.25 Silicon Germanium Transistor Emitter-Base Design 905
20.26 Epitaxial-Base Hetero-Junction Bipolar Transistor (HBT) Emitter-Base Design 907
20.27 Self-aligned Silicon Germanium HBT Device 907
20.28 Non-Self Aligned Silicon Germanium HBT 908
20.29 Emitter-Base Design RF Frequency Performance Metrics 908
20.30 SiGe HBT Emitter-Base Resistance Model 909
20.31 SiGe HBT Emitter-Base Design and Silicide Placement 909
20.32 Silicide Material and ESD 910
20.33 Titanium Silicide and ESD 911
20.34 Cobalt Salicide 913
20.35 Self-aligned (SA) Emitter Base Design 914
20.36 Non-Self Aligned (NSA) Emitter Base Design 917
20.37 Non-Self Aligned HBT Human Body Model (HBM) Step Stress 918
20.38 Transmission Line Pulse (TLP) Step Stress 918
20.39 RF Testing of SiGe HBT Emitter-Base Configuration 921
20.40 Unity Current Gain Cutoff Frequency - Collector Current Plots 923
20.41 f MAX and f T 924
20.42 Electrothermal Simulation of Emitter-Base Stress 925
20.43 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data 926
20.44 Silicon Germanium HBT Multiple-emitter Study 927
20.45 RF ESD Design Practice 927
20.46 Silicon Germanium ESD Failure Mechanisms 928
20.47 Summary and Closing Comments 928
References 928
21 ESD in Silicon Germanium Carbon 935
21.1 Heterojunctions and Silicon Germanium Carbon Technology 935
21.2 Silicon Germanium Carbon 935
21.3 Silicon Germanium Carbon Collector-Emitter ESD Measurements 937
21.4 Silicon Germanium Transistor Emitter-Base Design 940
21.5 Silicon Germanium Carbon - ESD-Induced S-Parameter Degradation 943
21.6 Silicon Germanium Carbon ESD Failure Mechanisms 945
21.7 Summary and Closing Comments 945
References 946
22 ESD in GaAs 951
22.1 Gallium Arsenide Technology and ESD 951
22.2 Gallium Arsenide Energy-to-Failure, and Power-to-Failure 951
22.3 Gallium Arsenide ESD Failures in Active and Passive Elements 954
22.4 Gallium Arsenide HBT Devices and ESD 955
22.5 Gallium Arsenide HBT Device ESD Results 956
22.6 Gallium Arsenide HBT Diode Strings 957
22.7 Gallium Arsenide HBT-based Passive Elements 959
22.8 GaAs HBT Base-Collector Varactor 959
22.9 Gallium Arsenide Technology Table of Failure Mechanisms 960
22.10 Application - GaAs Power Amplifier in a Cell Phone 961
22.11 Summary and Closing Comments 965
Questions 965
References 966
23 ESD in Bulk and SOI FINFET 971
23.1 Early FinFET Structures 971
23.2 FinFET Structure and Design Parameters 971
23.3 FinFET Parameters 973
23.4 Summary and Closing Comments 977
References 977
24 MEMs 979
24.1 Micro-electromechanical (MEM) Devices 979
24.2 ESD Concerns in Micro-electromechanical (MEM) Devices 980
24.3 Actuators 982
24.5 Micro-electromechanical (MEM) Mirrors 985
24.6 Summary and Closing Comments 989
References 989
25 Magnetic Recording 991
25.1 Magnetic Recording Technology 991
25.2 Summary and Closing Comments 995
References 995
26 Photomasks 1003
26.1 Photomasks and Reticles 1003
26.2 ESD Concerns in Photomasks 1003
26.3 Avalanche Breakdown in Photomasks 1004
26.4 Electrical Model in Photomasks 1007
26.5 Failure Defects in Photomasks 1008
26.6 Summary and Closing Comments 1011
References 1011
Appendix Table of Acronyms 1013
A Glossary of Terms - EMC Terminology 1015
B Appendix B. ESD Standards 1017
B.1 ESD Association 1017
B.2 International Organization of Standards 1018
B.3 Department of Defense 1018
B.4 Military Standards 1019
B.5 Airborne Standards and Lightning 1019
C Index 1021
D Wiley Series in Electrostatic Discharge (ESD) and Electrical Overstress (EOS) 1055
D.1 Additional Wiley Texts 1055
E ESD Design Rules 1057
E.1 ESD Design Rule Check (DRC) 1057
E.2 Electrostatic Discharge (ESD) Layout Versus Schematic (LVS) Verification 1058
E.3 ESD Electrical Rule Check (ERC) 1059
F Guard Ring Design Rules 1061
F.1 Latchup Design Rule Checking (DRC) and Guard Rings 1061
F.2 Latchup Electrical Rule Check (ERC) 1063
F.3 Guard Ring Resistance 1064
G EOS Design Rules and Checklist 1067
G.1 Electrical Overstress (EOS) Design Rule Checking 1067
G.2 Electrical Overstress (EOS) Layout Versus Schematic (LVS) Verification 1067
G.3 Electrical Overstress (EOS) Electrical Rule Check (ERC) 1068
H Latchup Design Rules 1069
H.1 Latchup Design Rule Checking (DRC) 1069
H.2 Latchup Electrical Rule Check (ERC) 1072
I ESD Cookbook 1077
I.1 Electrostatic Discharge (ESD) Cookbook 1077
J EOS Cookbook 1079
J.1 Electrical Overstress (EOS) Cookbook 1079
K Latchup Cookbook 1081
K.1 Latchup Design Rule Checking (DRC) 1081
K.2 Latchup Electrical Rule Check (ERC) 1083
L ESD Design and Release Check List 1087
L.1 ESD Design Release 1087
L.2 Electrostatic Discharge (ESD) Checklists 1087
M EOS Design and Release Checklist 1089
M.1 Electrical Overstress (EOS) and ESD Design Release 1089
M.2 Electrical Overstress (EOS) Design Release Process 1089
M.3 Electrical Overstress (EOS) Checklists 1090
M.4 An EOS Checklist 1091
N Latchup Design and Release Checklist 1093
N.1 Latchup Design Rule Checking (DRC) 1093
N.2 Latchup Electrical Rule Checking (ERC) 1095
N.3 Latchup Checklists 1095
N.4 A Latchup Design and Release Checklist 1096
Index 1097
