Ahmed Pipelined ADC Design and Enhancement Techniques

1. Auflage 2010
ISBN: 978-90-481-8652-5
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 200 Seiten

Reihe: Analog Circuits and Signal Processing

Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.

Autoren/Hrsg.

Ahmed, Imran

Inhaltsverzeichnis

1;Preface;6
2;Contents;8
3;Chapter 1: Introduction;23
3.1;Overview;23
3.2;Chapter Outline;25
3.2.1;Section I: Pipelined ADC Design;25
3.2.2;Section II: Pipelined ADC Enhancement Techniques;26
4;Part I: Pipelined ADC Design;27
4.1;Chapter 2: ADC Architectures;28
4.1.1;Overview;28
4.1.2;Factors Which Determine ADC Resolution and Linearity;28
4.1.3;ADC Architectures;32
4.1.4;ADC Figure-of-Merit;33
4.1.5;Flash ADC;33
4.1.6;SAR ADC;35
4.1.7;Sub-samplingsub-sampling;37
4.1.8;Summary;38
4.2;Chapter 3: Pipelined ADC Architecture Overview;39
4.2.1;Overview;39
4.2.2;Pipelined ADC Introduction;39
4.2.3;Multiplying Digital to Analog Converter (MDAC);41
4.2.4;Opamp DC Gain Requirements;43
4.2.5;Opamp Bandwidth Requirements;46
4.2.6;Thermal Noise Requirements;48
4.2.7;MDAC Design: Capacitor Matching/Linearity;49
4.2.8;Error Correction in Pipelined ADCs: Relaxed Sub-ADC Requirements;51
4.2.9;Sub-ADC Design: Comparator;55
4.2.10;Front-End Sample-and-Hold;56
4.2.11;Summary;58
4.3;Chapter 4: Scaling Power with Sampling Rate in an ADC;59
4.3.1;Overview;59
4.3.2;ADC Power as a Function of Sampling Rate;59
4.3.3;Digital Versus Analog Power;60
4.3.4;Weak Inversion Model: EKV;62
4.3.5;Weak Inversion Issues: Mismatch;63
4.3.6;Current Scaling: Multiple Design Corners;65
4.3.7;Current Scaling: Bias Point Sensitivity;65
4.3.8;Current Scaling: IR Drops;66
4.3.9;Summary;68
4.4;Chapter 5: State of the Art Pipelined ADC Design;69
4.4.1;Overview;69
4.4.2;Calibrationcalibration in Pipelined ADCs;69
4.4.2.1;Review of Error Sources;70
4.4.2.2;Gaincalibrationgain error correction Error Correction;70
4.4.2.3;DAC Error Correction;72
4.4.2.4;Foreground Calibration;72
4.4.2.5;Background Calibration;73
4.4.2.6;Rapid Calibrationrapid calibration of ADC Errors;74
4.4.3;Power Scalability with Respect to Sampling Rate;76
4.4.4;Power Reduction Techniques in Pipelined ADCs;76
4.4.4.1;Front-End S/H Removal;76
4.4.4.2;Open-Loop Amplifier Approach;78
4.4.4.3;Comparator Based Switched Capacitor Circuits;80
4.4.5;Summary;81
5;Part II: Pipelined ADC Enhancement Techniques;82
5.1;Chapter 6: Rapid Calibration of DAC and Gain Errors in a Multi-bit Pipeline Stage;83
5.1.1;Overview;83
5.1.2;Motivation;83
5.1.2.1;Why Are DAC Errors Important to Correct?;84
5.1.3;Rapid DAC + Gain Calibration Architecture;84
5.1.3.1;Measurement of Missing Codes Due to DAC and Gain Errors;85
5.1.3.2;Correction of Missing Codes;86
5.1.3.3;Mismatch Between ADCs;87
5.1.3.4;Simulationsimulation resultsrapid calibration ADC Results;88
5.1.4;Circuit Implementation;91
5.1.4.1;Front-End Sample-and-Hold;92
5.1.4.2;5-Bit Flash ADC;93
5.1.4.3;4-Bit MDAC;93
5.1.4.4;Backend Pipelined ADC;95
5.1.4.5;Digital Calibration;96
5.1.5;Testing;96
5.1.5.1;PCB;97
5.1.5.2;Test Setup;97
5.1.6;Measured Results;99
5.1.6.1;INL/DNL Plots;99
5.1.6.2;SNDR/SFDR Plots;99
5.1.6.3;Calibration Time;100
5.1.7;Summary;102
5.2;Chapter 7: A Power Scalable and Low Power Pipelined ADC;103
5.2.1;Overview;103
5.2.2;Power Scalablepower scalable Architecture;103
5.2.3;Current Modulated Power Scaling (CMPS);106
5.2.4;Current Switching Issues;109
5.2.5;Hybrid Power Scalinghybrid power scaling;110
5.2.6;Detailed Trigger Analysis;111
5.2.7;Design of the Digital State Machine;115
5.2.8;Rapid Power-On Opampsrapid power-on op118
5.2.8.1;Conventional Approach: Switched Bias Opampswitched bias op118
5.2.8.2;Rapid Power-On Opampsrapid power-on opamp Used in This Work;119
5.2.8.3;Benefitsgain boosting of Feedback Based Biasing: Increased Output Resistance;122
5.2.8.4;Opampopamp Specification/Characterization;123
5.2.9;Common Mode Feed Back (CMFBCMFB) for Rapid Power-On Op127
5.2.10;Power Reduction Through Current Modulationcurrent modulation;129
5.2.10.1;Common Mode Feed Back (CMFBCMFB) for Different Opamp Modes;130
5.2.11;Sample-and-Hold (S/HS/H);131
5.2.12;1.5-bit MDACMDAC;132
5.2.13;Sub-ADCsub-ADC Comparatorscomparator;132
5.2.14;Bias Circuitsbias circuits;133
5.2.15;Non-overlapping Clock Generatornon overlapping clock generator;134
5.2.16;Reference voltagesreference voltages;135
5.2.17;Digital Error Correctiondigital error correction;136
5.2.18;Experimental Implementation: PCBPCB;136
5.2.19;Experimental Implementation: Test Setuptest setup;136
5.2.20;Measured Resultsmeasured results;138
5.2.21;Current Scaledcurrent scaling Power;139
5.2.21.1;Power Reduction Mode: Static Accuracy;145
5.2.21.2;Power Scalable ADC: Current Scalingcurrent scaling;149
5.2.22;Power Scalable ADC: Power Scaling Usingty CMPSCMPS;155
5.2.23;Summary;162
5.3;Chapter 8: A Sub-sampling ADC with Embedded Sample-and-Hold;164
5.3.1;Overview;164
5.3.2;Motivationsub-sampling;164
5.3.3;Embedded S/HS/Hremoval Technique;165
5.3.4;Circuit Implementation;168
5.3.4.1;ADC Architecture;168
5.3.4.2;Rapid Power-On Op169
5.3.4.3;Generation of Delayed Clock Phi2D;170
5.3.5;Test Setup: PCBPCB;172
5.3.6;Test Setuptest setup: Equipment;173
5.3.7;Measured Results;173
5.3.7.1;SNDR Versus Input Frequency;174
5.3.7.2;Power Versus Sampling Rate;175
5.3.7.3;Tdelay Versus Settling Time: Robustness of Technique;176
5.3.8;Summary;177
5.4;Chapter 9: A Capacitive Charge Pump Based Low Power Pipelined ADC;179
5.4.1;Overview;179
5.4.2;Motivation;180
5.4.3;Architecture: Capacitive Charge Pump Based Gain;180
5.4.4;Effect of Parasitic Capacitors;184
5.4.5;Unity Gain Buffer Topology;186
5.4.5.1;Linesource followerlinearityarity of Source Follower in a Sampled System;191
5.4.5.2;Signal Swing of Source Followersource followersignal swing;192
5.4.6;Noise Analysis of Capacitive Charge Pump Based MDAC;193
5.4.7;Calibration of Pipeline Stages;197
5.4.7.1;Foreground Calibrationforeground calibration in Detail;197
5.4.8;Theoretical Power SavingsTheoretical power savings capacitive charge pumptheoretical power savings;199
5.4.9;Design Specifications;201
5.4.10;Circuit Design;202
5.4.10.1;ADC Top Level Topology;202
5.4.10.2;Front-End Sample-and-HoldS/Hwithout op203
5.4.10.3;MDACMDAC and Unity Gain Amplifier;203
5.4.10.4;Sub-ADCsub-ADC;205
5.4.10.5;Digital State Machine;206
5.4.10.6;Analog Test-Muxanalog test-mux;206
5.4.11;Testing;207
5.4.11.1;PCBPCB;207
5.4.11.2;Test Setuptest setup;207
5.4.12;Measured Results;209
5.4.12.1;Measured ADC SNDR Variation;210
5.4.12.2;ADC FFTs;212
5.4.12.3;INL/DNL plots;215
5.4.13;Summary;215
5.5;Chapter 10: Summary;216
5.5.1;Summary;216
6;References;218
7;Index;223