Circuit Synthesis with VHDL

1. Auflage 1994
ISBN: 978-0-7923-9429-7
Verlag: Springer US

Buch, Englisch, Band 261, 221 Seiten, Format (B × H): 160 mm x 241 mm, Gewicht: 1150 g

Reihe: The Springer International Series in Engineering and Computer Science

One of the main applications of VHDL is the synthesis of electronic circuits. is an introduction to the use of VHDL logic (RTL) synthesis tools in circuit design. The modeling styles proposed are independent of specific market tools and focus on constructs widely recognized as synthesizable by synthesis tools.
A statement of the prerequisites for synthesis is followed by a short introduction to the VHDL concepts used in synthesis. presents two possible approaches to synthesis: the first starts with VHDL features and derives hardware counterparts; the second starts from a given hardware component and derives several description styles. The book also describes how to introduce the synthesis design cycle into existing design methodologies and the standard synthesis environment.
concludes with a case study providing a realistic example of the design flow from behavioral description down to the synthesized level.
is essential reading for all students, researchers, design engineers and managers working with VHDL in a synthesis environment.

Zielgruppe

Research

Autoren/Hrsg.

Airiau, Roland

Olive, Vincent

Bergé, Jean-Michel

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf
• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Geisteswissenschaften Design Produktdesign, Industriedesign
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Mathematik | Informatik EDV | Informatik Informatik

Inhaltsverzeichnis

1. ABOUT SYNTHESIS.- 1.1. Why VHDL?.- 1.2. VHDL for Which Purpose’?.- 1.3. Is VHDL a Good Language for Synthesise.- 1.4. A Book, an Outline.- 1.5. Synthesis Domain.- 1.6. Interests of Synthesis.- 1.7. Architectural Synthesis Versus Logic Synthesis.- 1.8. Consistency Between Simulation and Synthesis.- 2. VHDL CONCEPTS.- 2.1. Philosophy of the Language.- 2.2. Hardware Hierarchy.- 2.3. Software Hierarchy.- 2.4. Objects of the Language.- 2.5. Information Representation.- 2.6. Concurrency.- 2.7. Sequential Domain.- 2.8. Attached Characteristics.- 2.9. Predefined Environment.- 3. MAPPING VHDL TO HARDWARE.- 3.1. Synthesis Modeling Style.- 3.2. VHDL Types.- 3.3. VHDL Objects.- 3.4. Sequential Statements.- 3.5. Concurrent Statements.- 3.6. Using Generics.- 3.7. Conclusion.- 4. MAPPING HARDWARE TO VHDL.- 4.1. Combinational Circuits.- 4.2. Synchronous Circuits.- 5. DESIGN METHODOLOGY.- 5.1. Synthesis Design Cycle.- 5.2. Synthesis Process Control.- 6. SYNTHESIS STANDARD ENVIRONMENT.- 6.1. Principle.- 6.2. Package STD_LOGIC_1164.- 6.3. Synthesis Working Group Results.- 7. CASE STUDY.- 7.1. Traffic Light Controller: Once Again?.- 7.2. Specification of the Problem.- 7.3. Entity Declaration.- 7.4. Describing the Behavioral Architecture.- 7.5. Describing the Synthesizable Architecture.- 7.6. Designer’s Concerns.- 8. APPENDIX.- 8.1. Grammar Summary.- 8.2. Memo.- 8.3 Index.