Delgado Kloos / Breuer Formal Semantics for VHDL

1995
ISBN: 978-1-4615-2237-9
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 307, 249 Seiten, eBook

Reihe: The Springer International Series in Engineering and Computer Science

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic.
If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.

Zielgruppe

Research

Autoren/Hrsg.

Delgado Kloos, Carlos

Breuer, P.

Inhaltsverzeichnis

Foreword. Preface. 0. Giving Semantics to VHDL: an Introduction; C. Delgado Kloos, P.T. Breuer. 1. A Functional Semantics for Delta-Delay VHDL Based on Focus; M. Fuchs, M. Mendler. 2. A Functional Semantics for Unit-Delay VHDL; P.T. Breuer, L. Sánchez Fernanández, C. Delgado Kloos. 3. An Operational Semantics for a Subset of VHDL; J.P. Van Tassel. 4. A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines; E. Börger, U. Glässer, W. Müller. 5. A Formal Model of VHDL Using Coloured Petri Nets; S. Olcoz. 6. A Deterministic Finite-State Model for VHDL; G. Döhmen, R. Herrmann. 7. A Flow Graph Semantics of VHDL: a Basis for Hardware Verification with VHDL; R. Reetz, T. Kropf. References.