High Level Synthesis of ASICs under Timing and Synchronization Constraints

1. Auflage. Softcover version of original hardcover Auflage 1992
ISBN: 978-1-4419-5129-8
Verlag: Springer US

Buch, Englisch, Band 177, 294 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 476 g

Reihe: The Springer International Series in Engineering and Computer Science

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers.
addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where design is of utmost importance. In contrast, ASIC designs are often characterized by complex schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book.
Three requirements are important in modeling ASIC designs: , and The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

Zielgruppe

Research

Autoren/Hrsg.

Demicheli, Giovanni

Ku, David C.

Fachgebiete

• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren

Inhaltsverzeichnis

1 Introduction.- 2 System Overview.- 3 Behavioral Transformations.- 4 Sequencing Graph and Resource Model.- 5 Design Space Exploration.- 6 Relative Scheduling.- 7 Resource Conflict Resolution.- 8 Relative Control Generation.- 9 Relative Control Optimization.- 10 System Implementation.- 11 Experimental Results.- 12 Conclusions and Future Work.- References.