Debugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Here, a simple reporting of a failure is not enough, anymore. Rather, it becomes more and more important not only to find many errors early during development but also to provide efficient methods for their isolation. In the state-of-the-art of modeling and verification of ESL designs is reviewed. There, a particular focus is taken onto SystemC. Then, a reasoning hierarchy is introduced. The hierarchy combines well-known debugging techniques with whole new techniques to improve the verification efficiency at ESL. The proposed systematic debugging approach is supported amongst others by static code analysis, debug patterns, dynamic program slicing, design visualization, property generation, and automatic failure isolation. All techniques were empirically evaluated using real-world industrial designs. Summarized, the introduced approach enables a systematic search for errors in ESL designs. Here, the debugging techniques improve and accelerate error detection, observation, and isolation as well as design understanding.
Drechsler / Rogin
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Weitere Infos & Material
List of Figures. List of Tables. Preface. Acknowledgements.
1. INTRODUCTION. 2. ESL DESIGN AND VERIFICATION. 3. EARLY ERROR DETECTION. 4. HIGH-LEVEL DEBUGGING AND EXPLORATION. 5. LEARNING ABOUT THE DESIGN. 6. ISOLATING FAILURE CAUSES. 7. SUMMARY AND CONCLUSION. Appendix A. FDC Language. Appendix B. Debug Pattern Catalog.- References. List of Acronyms. Index of Symbols. Index.
