Jakushokas / Popovich / Mezhiba Power Distribution Networks with On-Chip Decoupling Capacitors

2. Auflage 2011
ISBN: 978-1-4419-7871-4
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 644 Seiten

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this second edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

Autoren/Hrsg.

Jakushokas, Renatas

Popovich, Mikhail

Mezhiba, Andrey V.

Köse, Selçuk

Friedman, Eby G.

Inhaltsverzeichnis

1;Contents;8
2;1 Preface to the Second Edition;20
3;2 Preface to the First Edition;24
4;Part I General Background;28
4.1;1 Introduction;31
4.1.1;1.1 Evolution of integrated circuit technology;33
4.1.2;1.2 Evolution of design objectives;36
4.1.3;1.3 The problem of power distribution;40
4.1.4;1.4 Deleterious effects of power distribution noise;46
4.1.4.1;1.4.1 Signal delay uncertainty;47
4.1.4.2;1.4.2 On-chip clock jitter;47
4.1.4.3;1.4.3 Noise margin degradation;50
4.1.4.4;1.4.4 Degradation of gate oxide reliability;50
4.1.5;1.5 Summary;51
4.2;2 Inductive Properties of Electric Circuits;52
4.2.1;2.1 Definitions of inductance;53
4.2.1.1;2.1.1 Field energy definition;53
4.2.1.2;2.1.2 Magnetic flux definition;55
4.2.1.3;2.1.3 Partial inductance;60
4.2.1.4;2.1.4 Net inductance;65
4.2.2;2.2 Variation of inductance with frequency;68
4.2.2.1;2.2.1 Uniform current density approximation;69
4.2.2.2;2.2.2 Inductance variation mechanisms;70
4.2.2.2.1;Skin effect;70
4.2.2.2.2;Proximity effect;70
4.2.2.2.3;Multi-path current redistribution;72
4.2.2.3;2.2.3 Simple circuit model;74
4.2.3;2.3 Inductive behavior of circuits;77
4.2.4;2.4 Inductive properties of on-chip interconnect;79
4.2.5;2.5 Summary;83
4.3;3 Properties of On-Chip Inductive Current Loops;84
4.3.1;3.1 Introduction;84
4.3.2;3.2 Dependence of inductance on line length;85
4.3.3;3.3 Inductive coupling between two parallel loop segments;92
4.3.4;3.4 Application to circuit analysis;93
4.3.5;3.5 Summary;94
4.4;4 Electromigration;96
4.4.1;4.1 Physical mechanism of electromigration;97
4.4.2;4.2 Electromigration-induced mechanical stress;100
4.4.3;4.3 Steady state limit of electromigration damage;101
4.4.4;4.4 Dependence of electromigration lifetime on the line dimensions;103
4.4.5;4.5 Statistical distribution of electromigration lifetime;106
4.4.6;4.6 Electromigration lifetime under AC current;107
4.4.7;4.7 A comparison of aluminum and copper interconnect technologies;108
4.4.8;4.8 Designing for electromigration reliability;111
4.4.9;4.9 Summary;111
4.5;5 Decoupling Capacitance;113
4.5.1;5.1 Introduction to decoupling capacitance;114
4.5.1.1;5.1.1 Historical retrospective;114
4.5.1.2;5.1.2 Decoupling capacitor as a reservoir of charge;115
4.5.1.3;5.1.3 Practical model of a decoupling capacitor;117
4.5.2;5.2 Impedance of power distribution system with decoupling capacitors;121
4.5.2.1;5.2.1 Target impedance of a power distribution system;121
4.5.2.2;5.2.2 Antiresonance;124
4.5.2.3;5.2.3 Hydraulic analogy of hierarchical placement of decoupling capacitors;128
4.5.2.3.1;Fully compensated system;132
4.5.3;5.3 Intrinsic vs intentional on-chip decoupling capacitance;133
4.5.3.1;5.3.1 Intrinsic decoupling capacitance;134
4.5.3.2;5.3.2 Intentional decoupling capacitance;138
4.5.4;5.4 Types of on-chip decoupling capacitors;140
4.5.4.1;5.4.1 Polysilicon-insulator-polysilicon (PIP) capacitors;141
4.5.4.2;5.4.2 MOS capacitors;143
4.5.4.2.1;Accumulation;145
4.5.4.2.2;Depletion;146
4.5.4.2.3;Inversion;147
4.5.4.3;5.4.3 Metal-insulator-metal (MIM) capacitors;151
4.5.4.4;5.4.4 Lateral flux capacitors;153
4.5.4.4.1;Fractal capacitors;153
4.5.4.4.2;Woven capacitors;156
4.5.4.4.3;Vertical parallel plate (VPP) capacitors;156
4.5.4.5;5.4.5 Comparison of on-chip decoupling capacitors;157
4.5.5;5.5 On-chip switching voltage regulator;159
4.5.6;5.6 Summary;161
4.6;6 Scaling Trends of On-Chip Power Distribution Noise;163
4.6.1;6.1 Scaling models;164
4.6.2;6.2 Interconnect characteristics;166
4.6.2.1;6.2.1 Global interconnect characteristics;168
4.6.2.2;6.2.2 Scaling of the grid inductance;168
4.6.2.3;6.2.3 Flip-chip packaging characteristics;169
4.6.2.4;6.2.4 Impact of on-chip capacitance;171
4.6.3;6.3 Model of power supply noise;172
4.6.4;6.4 Power supply noise scaling;174
4.6.4.1;6.4.1 Analysis of constant metal thickness scenario;174
4.6.4.2;6.4.2 Analysis of the scaled metal thickness scenario;175
4.6.4.3;6.4.3 ITRS scaling of power noise;177
4.6.5;6.5 Implications of noise scaling;181
4.6.6;6.6 Summary;182
4.7;7 Conclusions;183
5;Part II Design of Power Systems;184
5.1;8 High Performance Power Distribution Systems;187
5.1.1;8.1 Physical structure of a power distribution system;188
5.1.2;8.2 Circuit model of a power distribution system;189
5.1.3;8.3 Output impedance of a power distribution system;192
5.1.4;8.4 A power distribution system with a decoupling capacitor;195
5.1.4.1;8.4.1 Impedance characteristics;195
5.1.4.2;8.4.2 Limitations of a single-tier decoupling scheme;199
5.1.5;8.5 Hierarchical placement of decoupling capacitance;201
5.1.5.1;Board decoupling capacitors;201
5.1.5.2;Package decoupling capacitors;202
5.1.5.3;On-chip decoupling capacitors;205
5.1.5.4;Advantages of hierarchical decoupling;205
5.1.6;8.6 Resonance in power distribution networks;208
5.1.7;8.7 Full impedance compensation;214
5.1.8;8.8 Case study;216
5.1.9;8.9 Design considerations;219
5.1.9.1;8.9.1 Inductance of the decoupling capacitors;219
5.1.9.2;8.9.2 Interconnect inductance;220
5.1.10;8.10 Limitations of the one-dimensional circuit model;221
5.1.11;8.11 Summary;224
5.2;9 On-Chip Power Distribution Networks;225
5.2.1;9.1 Styles of on-chip power distribution networks;226
5.2.1.1;9.1.1 Basic structure of on-chip power distribution networks;226
5.2.1.1.1;Routed networks;226
5.2.1.1.2;Mesh networks;226
5.2.1.1.3;Grid structured networks;227
5.2.1.1.4;Power and ground planes;229
5.2.1.1.5;Cascaded power/ground rings;230
5.2.1.1.6;Hybrid-structured networks;230
5.2.1.2;9.1.2 Improving the impedance characteristics of on-chip power distribution networks;231
5.2.1.3;9.1.3 Evolution of power distribution networks in Alpha microprocessors;232
5.2.1.3.1;Alpha 21064;233
5.2.1.3.2;Alpha 21164;233
5.2.1.3.3;Alpha 21264;234
5.2.2;9.2 Die-package interface;234
5.2.2.1;Wire-bond packaging;235
5.2.2.2;Flip-chip packaging;236
5.2.2.3;Future packaging solutions;239
5.2.3;9.3 Other considerations;239
5.2.3.1;Dependence of on-chip signal integrity on the structure of the power distribution network;240
5.2.3.2;Interaction between the substrate and the power distribution network;240
5.2.4;9.4 Summary;241
5.3;10 Computer-Aided Design and Analysis;242
5.3.1;10.1 Design flow for on-chip power distribution networks;243
5.3.1.1;Preliminary pre-floorplan design;243
5.3.1.2;Floorplan-based refinement;245
5.3.1.3;Layout-based verification;246
5.3.2;10.2 Linear analysis of power distribution networks;248
5.3.3;10.3 Modeling power distribution networks;250
5.3.3.1;Resistance of the on-chip power distribution network;251
5.3.3.2;Characterization of the on-chip decoupling capacitance;252
5.3.3.3;Inductance of the on-chip power distribution network;253
5.3.3.4;Exploiting symmetry to reduce model complexity;255
5.3.4;10.4 Characterizing the power current requirements of on-chip circuits;257
5.3.4.1;Preliminary evaluation of power current requirements;257
5.3.4.2;Gate level estimates of the power current requirements;258
5.3.5;10.5 Numerical methods for analyzing power distribution networks;259
5.3.5.1;Model partitioning in RC and RLC parts;260
5.3.5.2;Improving the initial condition accuracy of the AC analysis;260
5.3.5.3;Global-local hierarchical analysis;262
5.3.5.4;Random walk based technique;264
5.3.5.5;Multigrid analysis;265
5.3.5.6;Hierarchical analysis of networks with mesh-tree topology;265
5.3.5.7;Efficient analysis of RL trees;266
5.3.6;10.6 Allocation of on-chip decoupling capacitors;266
5.3.6.1;10.6.1 Charge-based allocation methodology;268
5.3.6.2;10.6.2 Allocation strategy based on the excessive noise amplitude;269
5.3.6.3;10.6.3 Allocation strategy based on excessive charge;270
5.3.7;10.7 Summary;272
5.4;11 Closed-Form Expressions for Fast IR Drop Analysis;274
5.4.1;11.1 Background of FAIR;275
5.4.2;11.2 Analytic IR drop analysis;277
5.4.2.1;11.2.1 One power supply and one current load;278
5.4.2.2;11.2.2 One power supply and multiple current loads;280
5.4.2.3;11.2.3 Multiple power supplies and one current load;281
5.4.2.4;11.2.4 Multiple power supplies and multiple current loads;284
5.4.3;11.3 Locality in power grid analysis;286
5.4.3.1;11.3.1 Principle of spatial locality in a power grid;286
5.4.3.2;11.3.2 Effect of spatial locality on computational complexity;290
5.4.3.3;11.3.3 Exploiting spatial locality in FAIR;291
5.4.3.4;11.3.4 Error correction windows;292
5.4.4;11.4 Experimental results;293
5.4.5;11.5 Summary;297
5.5;12 Conclusions;299
6;Part III Noise in Power Distribution Networks;300
6.1;13 Inductive Properties of On-Chip Power Distribution Grids;303
6.1.1;13.1 Power transmission circuit;303
6.1.2;13.2 Simulation setup;306
6.1.3;13.3 Grid types;306
6.1.4;13.4 Inductance versus line width;311
6.1.5;13.5 Dependence of inductance on grid type;312
6.1.5.1;13.5.1 Non-interdigitated versus interdigitated grids;312
6.1.5.2;13.5.2 Paired versus interdigitated grids;313
6.1.6;13.6 Dependence of Inductance on grid dimensions;314
6.1.6.1;13.6.1 Dependence of inductance on grid width;314
6.1.6.2;13.6.2 Dependence of inductance on grid length;316
6.1.6.3;13.6.3 Sheet inductance of power grids;316
6.1.6.4;13.6.4 Efficient computation of grid inductance;317
6.1.7;13.7 Summary;319
6.2;14 Variation of Grid Inductance with Frequency;320
6.2.1;14.1 Analysis approach;320
6.2.2;14.2 Discussion of inductance variation;322
6.2.2.1;14.2.1 Circuit models;322
6.2.2.2;14.2.2 Analysis of inductance variation;325
6.2.3;14.3 Summary;327
6.3;15 Inductance/Area/Resistance Tradeoffs;329
6.3.1;15.1 Inductance vs. resistance tradeoff under a constant grid area constraint;329
6.3.2;15.2 Inductance vs. area tradeoff under a constant grid resistance constraint;334
6.3.3;15.3 Summary;336
6.4;16 Inductance Model of Interdigitated Power and Ground Distribution Networks;338
6.4.1;16.1 Basic four-pair structure;339
6.4.2;16.2 Power and ground distribution network with a large number of interdigitated pairs;340
6.4.3;16.3 Comparison and discussion;345
6.4.4;16.4 Summary;349
6.5;17 On-Chip Power Noise Reduction Techniques;351
6.5.1;17.1 Ground noise reduction through an additional low noise on-chip ground;353
6.5.2;17.2 Dependence of ground bounce reduction on system parameters;355
6.5.2.1;17.2.1 Physical separation between noisy and noise sensitive circuits;356
6.5.2.2;17.2.2 Frequency and capacitance variations;357
6.5.2.3;17.2.3 Impedance of an additional ground path;359
6.5.3;17.3 Summary;360
6.6;18 Noise Issues in On-Chip Power Distribution Networks;362
6.6.1;18.1 Scaling effects in chip-package resonance;363
6.6.2;18.2 Propagation of power distribution noise;365
6.6.3;18.3 Local inductive behavior;368
6.6.4;18.4 Summary;372
6.7;19 Conclusions;373
7;Part IV Placement of On-Chip Decoupling Capacitance;374
7.1;20 Effective Radii of On-Chip Decoupling Capacitors;377
7.1.1;20.1 Background;379
7.1.2;20.2 Effective radius of on-chip decoupling capacitor based on target impedance;381
7.1.3;20.3 Estimation of required on-chip decoupling capacitance;383
7.1.3.1;20.3.1 Dominant resistive noise;384
7.1.3.2;20.3.2 Dominant inductive noise;385
7.1.3.3;20.3.3 Critical line length;388
7.1.4;20.4 Effective radius as determined by charge time;390
7.1.5;20.5 Design methodology for placing on-chip decoupling capacitors;396
7.1.6;20.6 Model of on-chip power distribution network;396
7.1.7;20.7 Case study;399
7.1.8;20.8 Design implications;405
7.1.9;20.9 Summary;406
7.2;21 Efficient Placement of Distributed On-Chip Decoupling Capacitors;408
7.2.1;21.1 Technology constraints;409
7.2.2;21.2 Placing on-chip decoupling capacitors in nanoscale ICs;410
7.2.3;21.3 Design of a distributed on-chip decoupling capacitor network;413
7.2.4;21.4 Design tradeoffs in a distributed on-chip decoupling capacitor network;418
7.2.4.1;21.4.1 Dependence of system parameters on R1;419
7.2.4.2;21.4.2 Minimum C1;420
7.2.4.3;21.4.3 Minimum total budgeted on-chip decoupling capacitance;421
7.2.5;21.5 Design methodology for a system of distributed on-chip decoupling capacitors;423
7.2.6;21.6 Case study;426
7.2.7;21.7 Summary;430
7.3;22 Simultaneous Co-Design of Distributed On-Chip Power Supplies and Decoupling Capacitors;432
7.3.1;22.1 Problem formulation;434
7.3.2;22.2 Simultaneous power supply and decoupling capacitor placement;435
7.3.3;22.3 Case study;437
7.3.4;22.4 Summary;441
7.4;23 Conclusions;442
8;Part V Multi-Layer Power Distribution Networks;443
8.1;24 Impedance Characteristics of Multi-Layer Grids;445
8.1.1;24.1 Electrical properties of multi-layer grids;447
8.1.1.1;24.1.1 Impedance characteristics of individual grid layers;447
8.1.1.2;24.1.2 Impedance characteristics of multi-layer grids;450
8.1.2;24.2 Case study of a two layer grid;452
8.1.2.1;24.2.1 Simulation setup;453
8.1.2.2;24.2.2 Inductive coupling between grid layers;453
8.1.2.3;24.2.3 Inductive characteristics of a two layer grid;457
8.1.2.4;24.2.4 Resistive characteristics of a two layer grid;458
8.1.2.5;24.2.5 Variation of impedance with frequency in a two layer grid;460
8.1.3;24.3 Design implications;461
8.1.4;24.4 Summary;462
8.2;25 Multi-Layer Interdigitated Power Distribution Networks;464
8.2.1;25.1 Single metal layer characteristics;466
8.2.1.1;25.1.1 Optimal width for minimum impedance;468
8.2.1.2;25.1.2 Optimal width characteristics;471
8.2.2;25.2 Multi-layer optimization;474
8.2.2.1;25.2.1 First approach - equal current density;475
8.2.2.2;25.2.2 Second approach - minimum impedance;481
8.2.3;25.3 Discussion;483
8.2.3.1;25.3.1 Comparison;483
8.2.3.2;25.3.2 Routability;484
8.2.3.3;25.3.3 Fidelity;487
8.2.3.4;25.3.4 Critical frequency;488
8.2.4;25.4 Summary;489
8.3;26 Conclusions;491
9;Part VI Multi-Voltage Power Network Systems;492
9.1;27 Multiple On-Chip Power Supply Systems;494
9.1.1;27.1 ICs with multiple power supply voltages;495
9.1.1.1;27.1.1 Multiple power supply voltage techniques;496
9.1.1.2;27.1.2 Clustered voltage scaling (CVS);498
9.1.1.3;27.1.3 Extended clustered voltage scaling (ECVS);499
9.1.2;27.2 Challenges in ICs with multiple power supply voltages;500
9.1.2.1;27.2.1 Die area;501
9.1.2.2;27.2.2 Power dissipation;501
9.1.2.3;27.2.3 Design complexity;502
9.1.2.4;27.2.4 Placement and routing;502
9.1.2.4.1;Area-by-area architecture;503
9.1.2.4.2;Row-by-row architecture;503
9.1.2.4.3;In-row architecture;503
9.1.3;27.3 Optimum number and magnitude of available power supply voltages;505
9.1.4;27.4 Summary;510
9.2;28 On-Chip Power Distribution Grids with Multiple Supply Voltages;512
9.2.1;28.1 Background;514
9.2.2;28.2 Simulation setup;515
9.2.3;28.3 Power distribution grid with dual supply and dual ground;517
9.2.4;28.4 Interdigitated grids with DSDG;520
9.2.4.1;28.4.1 Type I interdigitated grids with DSDG;520
9.2.4.2;28.4.2 Type II interdigitated grids with DSDG;522
9.2.5;28.5 Paired grids with DSDG;524
9.2.5.1;28.5.1 Type I paired grids with DSDG;525
9.2.5.2;28.5.2 Type II paired grids with DSDG;526
9.2.6;28.6 Simulation results;529
9.2.6.1;28.6.1 Interdigitated power distribution grids without decoupling capacitors;530
9.2.6.2;28.6.2 Paired power distribution grids without decoupling capacitors;537
9.2.6.3;28.6.3 Power distribution grids with decoupling capacitors;538
9.2.6.4;28.6.4 Dependence of power noise on the switching frequency of the current loads;542
9.2.7;28.7 Design implications;545
9.2.8;28.8 Summary;547
9.3;29 Decoupling Capacitors for Multi-Voltage Power Distribution Systems;549
9.3.1;29.1 Impedance of a power distribution system;551
9.3.1.1;29.1.1 Impedance of a power distribution system;552
9.3.1.2;29.1.2 Antiresonance of parallel capacitors;555
9.3.1.3;29.1.3 Dependence of impedance on power distribution system parameters;556
9.3.2;29.2 Case study of the impedance of a power distribution system;559
9.3.3;29.3 Voltage transfer function of power distribution system;564
9.3.3.1;29.3.1 Voltage transfer function of a power distribution system;564
9.3.3.2;29.3.2 Dependence of voltage transfer function on power distribution system parameters;566
9.3.4;29.4 Case study of the voltage response of a power distribution system;569
9.3.4.1;29.4.1 Overshoot-free magnitude of a voltage transfer function;571
9.3.4.2;29.4.2 Tradeoff between the magnitude and frequency range;573
9.3.5;29.5 Summary;577
9.4;30 Conclusions;578
10;Part VII Final Comments and Supplementary Material;579
10.1;Closing Remarks;580
11;Appendices;585
11.1;A Estimate of Initial Optimal Width for Interdigitated Power/Ground Network;586
11.2;B First Optimization Approach for Multi-Layer Interdigitated Power Distribution Network;587
11.3;C Second Optimization Approach for Multi-Layer Interdigitated Power Distribution Network;589
11.4;D Mutual Loop Inductance in Fully Interdigitated Power Distribution Grids with DSDG;590
11.5;E Mutual Loop Inductance in Pseudo-Interdigitated Power Distribution Grids with DSDG;592
11.6;F Mutual Loop Inductance in Fully Paired Power Distribution Grids with DSDG;594
11.7;G Mutual Loop Inductance in Pseudo-Paired Power Distribution Grids with DSDG;596
12;References;598
13;Index;626
14;About the Authors;631