E-Book, Englisch, 264 Seiten
Ma / Marchal / Scarpazza Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms
1. Auflage 2007
ISBN: 978-1-4020-6344-2
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark
E-Book, Englisch, 264 Seiten
ISBN: 978-1-4020-6344-2
Verlag: Springer Netherlands
Format: PDF
Kopierschutz: 1 - PDF Watermark
A genuinely useful text that gives an overview of the state-of-the-art in system-level design trade-off explorations for concurrent tasks running on embedded heterogeneous multiple processors. The targeted application domain covers complex embedded real-time multi-media and communication applications. This material is mainly based on research at IMEC and its international university network partners in this area over the last decade. In all, the material those in the digital signal processing industry will find here is bang up-to-date.
Francky Catthoor is a leading researcher at IMEC and is very well established within the EDA community. He is IEEE Fellow and has edited and authored 6 books for Springer/Kluwer.
Autoren/Hrsg.
Weitere Infos & Material
1;Preface;5
2;Contents;9
3;1 Introduction;13
3.1;1.1 The System-on-Chip Era;14
3.2;1.2 Characteristics of Embedded Software;17
3.3;1.3 Context and Motivation;21
3.4;1.4 TCM Framework;24
3.5;1.5 Overview of Chapters;25
4;2 Related Work;27
4.1;2.1 Real-time Scheduling;27
4.2;2.2 Low-power Considerations;34
4.3;2.3 Platform Issues and Codesign Framework;41
5;3 System Model and Work Flow;46
5.1;3.1 Overview of TCM Work flow;46
5.2;3.2 Gray-Box Model;48
5.3;3.3 System Scenario Selection;54
5.4;3.4 Two-Phase Scheduling;56
5.5;3.5 Summary;59
6;4 Basic Design-Time Scheduling;61
6.1;4.1 Problem Formulation;61
6.2;4.2 Exact Scheduling Algorithms;63
6.3;4.3 Forward Search Algorithm;65
6.4;4.4 Backward Search Algorithm;99
6.5;4.5 Subplatform Scheduling;108
6.6;4.6 Handling Timing-Constraints;114
6.7;4.7 Summary;117
7;5 Scalable Design-Time Scheduling;118
7.1;5.1 Introduction;118
7.2;5.2 Motivational Example;119
7.3;5.3 Thread Frame Decomposition;123
7.4;5.4 Thread Partition Clustering;132
7.5;5.5 Thread Partition Interleaving;133
7.6;5.6 Experimental Results and Discussions;137
7.7;5.7 Comparison with State of the Art;139
7.8;5.8 Summary;142
8;6 Fast and Scalable Run-time Scheduling;143
8.1;6.1 Two-Phase Task Scheduling: Why and How;143
8.2;6.2 Run-Time Scheduling Algorithm;149
8.3;6.3 Experimental Results;154
8.4;6.4 Summary;158
9;7 Handling of Multidimensional Pareto Curves;159
9.1;7.1 Overview of the Customized Run-Time Management;160
9.2;7.2 Problem Formulation of Run-Time Operating Point Selector;163
9.3;7.3 Related Work;164
9.4;7.4 MP-SoC Heuristic Description;165
9.5;7.5 Experimental Results;168
9.6;7.6 Summary;170
10;8 Run-Time Software Multithreading;171
10.1;8.1 Motivation of Run-Time Rescheduling;172
10.2;8.2 Run-Time Interleaving;174
10.3;8.3 Experimental Results and Discussion;181
10.4;8.4 Comparison with State of the Art;182
10.5;8.5 Summary;184
11;9 Fast Source-level Performance Estimation;185
11.1;9.1 Introduction;185
11.2;9.2 Motivational Example;187
11.3;9.3 Comparison with State of the Art;190
11.4;9.4 Fundamentals of the Estimation Technique;192
11.5;9.5 Experimental Results;199
11.6;9.6 Summary;201
12;10 Handling of Task-Level Data Communication and Storage;202
12.1;10.1 Memory Architecture;203
12.2;10.2 Exploring Thread Node Level Data Reuse;207
12.3;10.3 Data Assignment on L1 Memory Layer;208
12.4;10.4 Bandwidth Aware Scheduling;219
12.5;10.5 Handling inter-TN and inter-TF Data Transfers;226
12.6;10.6 Summary;230
13;11 Demonstration on Heterogeneous Multiprocessor SoCs;232
13.1;11.1 Motivation for Heterogeneous Multiprocessor Platforms;232
13.2;11.2 Mapping Visual Texture Coding Decoder;233
13.3;11.3 Summary;243
14;12 Conclusions and future research work;245
15;A Input and output data of scheduling examples in Section 4.3.1;249
16;References;254
