Shim / Shin Physical Design and Mask Synthesis for Directed Self-Assembly Lithography

1. Auflage 2018
ISBN: 978-3-319-76294-4
Verlag: Springer International Publishing
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 144 Seiten, eBook

Reihe: NanoScience and Technology

This book discusses physical design and mask synthesis of directed self-assembly lithography (DSAL). It covers the basic background of DSAL technology, physical design optimizations such as placement and redundant via insertion, and DSAL mask synthesis as well as its verification. Directed self-assembly lithography (DSAL) is a highly promising patterning solution in sub-7nm technology.

Zielgruppe

Research

Autoren/Hrsg.

Shim, Seongbo

Shin, Youngsoo

Inhaltsverzeichnis

1;Preface;7
2;Contents;9
3;Acronyms;12
4;1 Introduction;14
4.1;1.1 Optical Lithography;14
4.2;1.2 Next Generation Lithography Technologies;17
4.2.1;1.2.1 Extreme Ultraviolet Lithography (EUVL);17
4.2.2;1.2.2 Electron Beam Lithography (EBL);18
4.2.3;1.2.3 Nanoimprint Lithography (NIL);19
4.3;1.3 Directed Self-Assembly Lithography (DSAL);20
4.4;1.4 Overview of the Book;22
4.5;References;24
5;Part I Physical Design Optimizations;26
6;2 DSAL Manufacturability;27
6.1;2.1 DSA Defect;27
6.1.1;2.1.1 DSAL for IC Design and Fabrication;27
6.1.2;2.1.2 Lithography-Induced DSA Defect;29
6.2;2.2 DSA Defect Probability;30
6.2.1;2.2.1 Definition;30
6.2.2;2.2.2 Defect Probability Computation;32
6.3;2.3 Experimental Observations;33
6.4;2.4 Summary;35
6.5;References;35
7;3 Placement Optimization for DSAL;37
7.1;3.1 Introduction;37
7.2;3.2 Defect Probability of Cell Pair;39
7.3;3.3 Post-Placement Optimization;40
7.3.1;3.3.1 Cell Flipping;40
7.3.2;3.3.2 Cell Swapping and Flipping;42
7.4;3.4 Automatic Placement;43
7.4.1;3.4.1 Implementation of Placer;43
7.4.2;3.4.2 Considerations on Analytical Placer;46
7.5;3.5 Experiments;47
7.6;3.6 Summary;50
7.7;References;50
8;4 Post-Placement Optimization for MP-DSAL Compliant Layout;52
8.1;4.1 Introduction;52
8.2;4.2 MP-DSAL Decomposition;54
8.3;4.3 Post-Placement Optimization;56
8.3.1;4.3.1 MP-DSAL Decomposition of Standard Cells;56
8.3.2;4.3.2 Placement Optimization for Cell Row;56
8.3.3;4.3.3 Considerations of Interrow Conflict;58
8.4;4.4 Experiments;59
8.5;4.5 Summary;60
8.6;References;61
9;5 Redundant Via Insertion for DSAL;62
9.1;5.1 Introduction;62
9.2;5.2 Preliminaries;63
9.2.1;5.2.1 Defect Probability of Via Cluster;63
9.2.2;5.2.2 Basic Redundant Via Insertion;65
9.3;5.3 DSAL Redundant Via Insertion Algorithm;65
9.3.1;5.3.1 Graph Modeling;66
9.3.2;5.3.2 Heuristic Insertion Algorithm;67
9.4;5.4 Experiments;68
9.5;5.5 Summary;71
9.6;References;72
10;6 Redundant Via Insertion for MP-DSAL;73
10.1;6.1 Introduction;73
10.2;6.2 Simultaneous Optimization of Redundant Via and Via Cluster;75
10.2.1;6.2.1 ILP Formulation;75
10.2.2;6.2.2 Graph-Based Heuristic;77
10.3;6.3 Experiments;79
10.4;6.4 Summary;82
10.5;References;82
11;Part II Mask Synthesis and Optimizations;84
12;7 DSAL Mask Synthesis;85
12.1;7.1 Introduction;85
12.2;7.2 Inverse DSA;86
12.2.1;7.2.1 Numerical Results;90
12.3;7.3 Inverse Lithography;91
12.3.1;7.3.1 Approximation of Cost Gradient;93
12.3.2;7.3.2 Evaluation;95
12.4;7.4 Mask Design with Process Variations;96
12.4.1;7.4.1 Inverse DSA and Inverse Lithography;96
12.4.2;7.4.2 Insertion of DSA-Aware Assist Feature;97
12.4.3;7.4.3 Assessment;98
12.5;7.5 Summary;99
12.6;References;99
13;8 Verification of Guide Patterns;101
13.1;8.1 Introduction;101
13.2;8.2 Test GPs;103
13.2.1;8.2.1 Preparation of GPs;103
13.2.2;8.2.2 Evaluation of GP Coverage;106
13.3;8.3 Preparing a GP Using Geometric Parameters;106
13.3.1;8.3.1 Geometric Parameters;106
13.3.2;8.3.2 Principal Component Analysis;110
13.3.3;8.3.3 Experimental Observations;111
13.4;8.4 Constructing a Verification Function;113
13.5;8.5 Experimental Assessment;115
13.5.1;8.5.1 Choice of Parameters;116
13.5.2;8.5.2 Parameter Reduction;117
13.5.3;8.5.3 Comparison of GP Verification Methods;119
13.5.4;8.5.4 A Global Verification Function;120
13.6;8.6 Conclusions;121
13.7;References;122
14;9 Cut Optimization;124
14.1;9.1 Introduction;124
14.2;9.2 Preliminaries;126
14.2.1;9.2.1 Critical Cut Distances in MP-DSAL;126
14.2.2;9.2.2 Wire Extension: Impact on Circuit Timing;127
14.3;9.3 MP-DSAL Cut Optimization;128
14.3.1;9.3.1 ILP Formulation;128
14.3.2;9.3.2 Heuristic Algorithm;130
14.4;9.4 Experiments;133
14.5;9.5 Conclusion;135
14.6;References;136
15;10 Summary of The Book;138
15.1;References;140
16;Index;141

Über Autor(innen)

Seongbo Shim received B.S. and M.S. degrees in physics from Seoul National University, Korea, in 2004 and 2006 respectively, and a Ph.D. in electrical engineering from KAIST, Korea, in 2016. From 2006 to 2012, he was with the Semiconductor R&D Center, Samsung Electronics, where he was a Senior Engineer working on photolithography, computational lithography, optical proximity correction (OPC), and design for manufacturability (DFM) for advanced technologies. He has authored more than 40 papers on lithography, OPC, and DFM. He is the holder of 15 patents. His research interests include mask synthesis algorithms, VLSI CAD for the design-manufacturing interface, design technology co-optimization (DTCO) for emerging technologies, and machine learning for lithography optimizations.

Youngsoo Shin received B.S., M.S., and Ph.D. degrees in Electronics Engineering from Seoul National University, Korea. From 2001 to 2004, he was a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY, USA. In 2004, he joined the Department of Electrical Engineering, KAIST, Korea, where he is currently a professor. He has served as a Program Chair of ICCD in 2014 and VLSI-SoC in 2015, and as a General Chair of ASP-DAC in 2018. He is an associate editor of IEEE Transactions on CAD and IEEE Design and Test. He is an IEEE Fellow.