Smoszna Synchronous Precharge Logic

1. Auflage 2012
ISBN: 978-0-12-401707-8
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark

E-Book, Englisch, 112 Seiten

Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book covers the challenges faced by designers when using this logic style, including logic basics, timing, noise considerations, alternative topologies and more. In addition advanced topics such as skew tolerant design are covered in some detail. Overall this is a comprehensive view of precharge logic, which should be useful to graduate students and designers in the field alike. It might also be considered as a supplemental title for courses covering VLSI. - Comprehensive guide to precharge logic - Explains both the advantages and disadvantages to help engineers decide when to utilize precharge logic - Useful for engineers in a variety of industries

Marek Smoszna is a memory design engineer at NVIDIA Corporation. He was born in Poland in 1972. He received his BS and MS in electrical engineering from Rensselaer Polytechnic Institute in 1995 and 1996, respectively. He holds two patents in the area of memory design with several other patent applications filed. His interests include high speed circuit and memory design. When not doing circuit design he can be found with his children at the beach.

Autoren/Hrsg.

Smoszna, Marek

Inhaltsverzeichnis

1;Front Cover;1
2;Synchronous Precharge Logic;4
3;Copyright Page;5
4;Dedication;6
5;Contents;8
6;List of figures;12
7;List of tables;16
8;About the author;18
9;1 Precharge Logic Basics;20
9.1;1.1 Introduction;20
9.2;1.2 What Is Precharge Logic?;20
9.3;1.3 Why Is it Faster than Static Logic?;21
9.4;1.4 Advantages of Precharge Logic;23
9.5;1.5 What About Using Other Transistors?;26
9.6;1.6 Domino Logic;26
9.6.1;1.6.1 Need for Monotonic Signals;27
9.6.2;1.6.2 Domino Logic Gates;27
9.7;1.7 Keepers: Improving the Charge Storage;29
9.8;1.8 Final Comments;31
10;2 Timing;32
10.1;2.1 Clock Skew Penalty;32
10.2;2.2 Hold-Time Problem;33
10.3;2.3 Nonoverlapping Clocks;34
10.4;2.4 A Better Latch;35
10.5;2.5 Input Setup Criteria;36
10.6;2.6 Input Hold Criteria;36
10.7;2.7 Precharge Timing;37
10.8;2.8 Skew Tolerant Design;37
11;3 Transistor Sizing;40
11.1;3.1 Sizing the Pulldown Stack;40
11.2;3.2 Sizing of the Output Inverter;40
11.3;3.3 Logical Effort;41
11.4;3.4 Sizing of the Keeper Device;41
11.4.1;3.4.1 PFET Keeper;42
11.4.2;3.4.2 NFET Keeper;43
11.4.3;3.4.3 Maximum Leakable NFET Width;43
11.5;3.5 Sizing of the Precharge Device;44
11.6;3.6 Sizing Precharge Gates with Wires;44
12;4 Noise Tolerance;46
12.1;4.1 Input-Connected Prechargers;46
12.2;4.2 Propagated Noise;47
12.3;4.3 Input Wire Noise;48
12.4;4.4 Supply-Level Variations;50
12.5;4.5 Charge Sharing;52
12.6;4.6 Charge Sharing: Example 1;53
12.7;4.7 Charge Sharing: Example 2;56
12.8;4.8 Leakage;58
12.9;4.9 Clock Coupling on the Internal Dynamic Node;59
12.10;4.10 Minority Carrier Charge Injection;60
12.11;4.11 Alpha Particles;60
12.12;4.12 Noise Induced on Dynamic Nodes Directly;61
12.13;4.13 Example of Transistor Crosstalk During Precharge;62
12.14;4.14 CSR Latch Signal Ordering;63
12.15;4.15 Interfacing to Transmission Gates;64
13;5 Topology Considerations;66
13.1;5.1 Limitation on Device Stacking;66
13.2;5.2 Limitation of Logic Width;66
13.3;5.3 Use of Low/High Vt Transistors;66
13.4;5.4 Sharing Evaluation Devices;67
13.5;5.5 Tapering of the Evaluation Device;68
13.6;5.6 Footed versus Unfooted;68
13.7;5.7 Compounding Outputs;71
13.8;5.8 Late Arriving Input on Top;73
13.9;5.9 Making Keepers Weak;73
13.10;5.10 Conditional Keepers;74
13.11;5.11 Placement of the Evaluation Device;75
14;6 Other Precharge Logic Styles;76
14.1;6.1 MODL;76
14.2;6.2 NORA Logic;76
14.3;6.3 Postcharge Logic;77
14.4;6.4 CD Domino;80
14.5;6.5 NTP Logic;81
14.6;6.6 Differential Cascode Voltage Switch Logic;81
14.7;6.7 DCML;83
14.8;6.8 SOI Precharge Logic;84
14.9;6.9 Advanced Work;85
15;7 Clocked Set–Reset Latches;88
15.1;7.1 Memory Special Cases;88
15.2;7.2 Building a CSR Latch;91
15.3;7.3 Time Borrowing;93
15.4;7.4 Hold-Time Margins;94
15.4.1;7.4.1 Margin 1;94
15.4.2;7.4.2 Margin 2;95
15.5;7.5 Mintime;95
15.6;7.6 Alternative Topology;96
15.7;7.7 The Other Phase;96
15.8;7.8 Two-Input Latch;96
15.9;7.9 Adding Scan;97
16;8 Layout Considerations;100
17;Appendix: Logical Effort;104
17.1;A.1 Derivation of Delay in a Logic Gate;104
17.2;A.2 The Logical Effort of a Single Stage;105
17.3;A.3 Multistage Networks;105
17.4;A.4 Minimum Delay;106
17.5;A.5 Best Number of Stages;107
18;References;108

Leseproben

List of figures

Figure 1.1

Basic precharged gate (NAND) with dynamic output

Figure 1.2

Clock phase definition

Figure 1.3

(A) Static transition HIGH to LOW; (B) precharge logic precharge and discharge

Figure 1.4

Precharge logic with latches

Figure 1.5

Transistor driving a wire load

Figure 1.6

Precharged NOR gate with a static inverter becomes an OR gate

Figure 1.7

Discharge of an output node due to an illegal input transition in an evaluation phase

Figure 1.8

Standard domino gate

Figure 1.9

Chain of two domino logic gates

Figure 1.10

Use of a “Keeper” to maintain charge on the dynamic node

Figure 1.11

Svensson style latch with a “Keeper.”

Figure 1.12

Use of both PMOS and NMOS Keepers

Figure 2.1

Diagram of clock phases

Figure 2.2

Hold-time failure at phase boundary

Figure 2.3

Nonoverlapping clock circuit diagram

Figure 2.4

Nonoverlapping clock timing

Figure 2.5

CSR latch placement at the end of precharge logic

Figure 2.6

CSR latch signal timing

Figure 2.7

Input signal setup requirements

Figure 2.8

Precharging internal capacitances

Figure 2.9

Two-phase overlapping clocks

Figure 2.10

Precharge time constraint

Figure 2.11

Evaluation time constraint

Figure 3.1

Keeper ratio diagram

Figure 3.2

Maximum leakable N-width calculation

Figure 3.3

Clock-gated NFET Keeper

Figure 4.1

Transfer characteristics of (A) static and (B) precharge logic

Figure 4.2

Input-connected precharger

Figure 4.3

Noise amplification

Figure 4.4

Capacitive coupling (A) and IR drops (B) in interconnect

Figure 4.5

Twisted wires to reduce noise

Figure 4.6

Ground bounce

Figure 4.7

System with a decoupling capacitor (A), and redrawn circuit for capacitor calculation (B)

Figure 4.8

Capacitances in a precharge gate

Figure 4.9

Internal node precharger

Figure 4.10

Not all nodes are a problem for charge sharing

Figure 4.11

Circuit for the example of charge sharing

Figure 4.12

Timing for the example of charge sharing

Figure 4.13

Circuit for the example of charge sharing, precharge network (A), and charge-sharing circuit (B)

Figure 4.14

Leakage paths

Figure 4.15

The stack effect to reduce leakage

Figure 4.16

Clock feedthrough

Figure 4.17

Minority carrier charge injection

Figure 4.18

Charge injection layout fix

Figure 4.19

Output transition back coupling to a dynamic node

Figure 4.20

Circuit for the example of transistor crosstalk

Figure 4.21

Timing for the example of transistor crosstalk

Figure 4.22

CSR latch

Figure 4.23

Dynamic latch discharge due to noise

Figure 5.1

LVT usage

Figure 5.2

Sharing the footer device

Figure 5.3

Not beneficial sharing of the footer device

Figure 5.4

Only the first domino gate needs a footer

Figure 5.5

Use of an evaluation footer in a multiple input gate

Figure 5.6

Footer sequence

Figure 5.7

D2 precharge timing requirements

Figure 5.8

Compounded wide OR

Figure 5.9

Compounded wide AND

Figure 5.10

Stacked Keepers

Figure 5.11

Conditional Keeper

Figure 5.12

Another conditional Keeper

Figure 5.13

Poorly designed precharge circuit

Figure 6.1

MODL circuit diagram

Figure 6.2

NORA logic

Figure 6.3

Postcharge logic gate

Figure 6.4

No evaluation device

Figure 6.5

Improved postcharge gate

Figure 6.6

CD domino logic chain

Figure 6.7

CD domino clock delay element

Figure 6.8

NTP logic gate

Figure 6.9

Dual-rail domino AND/NAND

Figure 6.10

Dual-rail domino XOR/XNOR

Figure 6.11

Dual-monotonic completion signal generation

Figure 6.12

DCML inverter

Figure 6.13

DCML voltage waveforms

Figure 6.14

DCML current source waveforms

Figure 6.15

SOI precharge gate

Figure 7.1

Domino logic with integral latch

Figure 7.2

Basic CSR latch

Figure 7.3

CSR latch timing

Figure 7.4

Memory Cases: (A) fully decoded address (one hot) and (B) regular encoded address. *, sync point

Figure 7.5

Basic dynamic latch

Figure...