Designing 2D and 3D Network-on-Chip Architectures

Softcover Nachdruck of the original 1. Auflage 2014
ISBN: 978-1-4939-4550-4
Verlag: Springer

Buch, Englisch, 265 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 4277 g

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Tatas, Konstantinos

Jantsch, Axel

Siozios, Kostas

Soudris, Dimitrios

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren

Inhaltsverzeichnis

Part I: Network-on-Chip Design Methodology.- Network-on-Chip Technology: A Paradigm Shift.- NoC Modeling and Topology Exploration.- Communication Architecture.- Power and Thermal Effects and Management.- NoC-based System Integration.- NoC Verification and Testing.- The Spidergon STNoC.- Middleware Memory Management in NoC.- On Designing 3-D Platforms.- The SYSMANTIC NoC Design and Prototyping Framework.- Part II: Suggested Projects.-  Projects on Network-on Chip.