Wang / Wu / Wen VLSI Test Principles and Architectures

Design for Testability
1. Auflage 2006
ISBN: 978-0-08-047479-3
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 808 Seiten, Web PDF

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
· Most up-to-date coverage of design for testability.
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

Autoren/Hrsg.

Wang, Laung-Terng

Wu, Cheng-Wen

Wen, Xiaoqing

Inhaltsverzeichnis

1;Front cover;1
2;Title page;6
3;Copyright page;7
4;Table of contents;8
5;Preface;22
6;In the Classroom;25
7;Acknowledgments;26
8;Contributors;28
9;About the Editors;30
10;1 Introduction;32
10.1;Importance of Testing;32
10.2;Testing During the VLSI Lifecycle;33
10.2.1;VLSI Development Process;34
10.2.1.1;Design Verification;35
10.2.1.2;Yield and Reject Rate;36
10.2.2;Electronic System Manufacturing Process;37
10.2.3;System-Level Operation;37
10.3;Challenges in VLSI Testing;39
10.3.1;Test Generation;40
10.3.2;Fault Models;42
10.3.2.1;Stuck-At Faults;43
10.3.2.2;Transistor Faults;46
10.3.2.3;Open and Short Faults;47
10.3.2.4;Delay Faults and Crosstalk;50
10.3.2.5;Pattern Sensitivity and Coupling Faults;51
10.3.2.6;Analog Fault Models;52
10.4;Levels of Abstraction in VLSI Testing;53
10.4.1;Register-Transfer Level and Behavioral Level;53
10.4.2;Gate Level;54
10.4.3;Switch Level;55
10.4.4;Physical Level;55
10.5;Historical Review of VLSI Test Technology;56
10.5.1;Automatic Test Equipment;56
10.5.2;Automatic Test Pattern Generation;58
10.5.3;Fault Simulation;59
10.5.4;Digital Circuit Testing;59
10.5.5;Analog and Mixed-Signal Circuit Testing;60
10.5.6;Design for Testability;60
10.5.7;Board Testing;62
10.5.8;Boundary Scan Testing;63
10.6;Concluding Remarks;64
10.7;Exercises;64
10.8;Acknowledgments;65
10.9;References;65
11;2 Design for Testability;68
11.1;Introduction;68
11.2;Testability Analysis;71
11.2.1;SCOAP Testability Analysis;72
11.2.1.1;Combinational Controllability and Observability Calculation;72
11.2.1.2;Sequential Controllability and Observability Calculation;74
11.2.2;Probability-Based Testability Analysis;76
11.2.3;Simulation-Based Testability Analysis;78
11.2.4;RTL Testability Analysis;79
11.3;Design for Testability Basics;81
11.3.1;Ad Hoc Approach;82
11.3.1.1;Test Point Insertion;82
11.3.2;Structured Approach;84
11.4;Scan Cell Designs;86
11.4.1;Muxed-D Scan Cell;86
11.4.2;Clocked-Scan Cell;87
11.4.3;LSSD Scan Cell;88
11.5;Scan Architectures;90
11.5.1;Full-Scan Design;90
11.5.1.1;Muxed-D Full-Scan Design;90
11.5.1.2;Clocked Full-Scan Design;93
11.5.1.3;LSSD Full-Scan Design;93
11.5.2;Partial-Scan Design;95
11.5.3;Random-Access Scan Design;98
11.6;Scan Design Rules;101
11.6.1;Tristate Buses;102
11.6.2;Bidirectional I/O Ports;102
11.6.3;Gated Clocks;102
11.6.4;Derived Clocks;105
11.6.5;Combinational Feedback Loops;105
11.6.6;Asynchronous Set/Reset Signals;106
11.7;Scan Design Flow;107
11.7.1;Scan Design Rule Checking and Repair;108
11.7.2;Scan Synthesis;109
11.7.2.1;Scan Configuration;110
11.7.2.2;Scan Replacement;113
11.7.2.3;Scan Reordering;113
11.7.2.4;Scan Stitching;114
11.7.3;Scan Extraction;114
11.7.4;Scan Verification;115
11.7.4.1;Verifying the Scan Shift Operation;116
11.7.4.2;Verifying the Scan Capture Operation;117
11.7.5;Scan Design Costs;117
11.8;Special-Purpose Scan Designs;118
11.8.1;Enhanced Scan;118
11.8.2;Snapshot Scan;119
11.8.3;Error-Resilient Scan;121
11.9;RTL Design for Testability;123
11.9.1;RTL Scan Design Rule Checking and Repair;124
11.9.2;RTL Scan Synthesis;125
11.9.3;RTL Scan Extraction and Scan Verification;126
11.10;Concluding Remarks;126
11.11;Exercises;127
11.12;Acknowledgments;130
11.13;References;130
12;3 Logic and Fault Simulation;136
12.1;Introduction;137
12.1.1;Logic Simulation for Design Verification;137
12.1.2;Fault Simulation for Test and Diagnosis;138
12.2;Simulation Models;139
12.2.1;Gate-Level Network;140
12.2.1.1;Sequential Circuits;140
12.2.2;Logic Symbols;141
12.2.2.1;Unknown State u;142
12.2.2.2;High-Impedance State Z;144
12.2.2.3;Intermediate Logic States;145
12.2.3;Logic Element Evaluation;145
12.2.3.1;Truth Tables;146
12.2.3.2;Input Scanning;146
12.2.3.3;Input Counting;147
12.2.3.4;Parallel Gate Evaluation;147
12.2.4;Timing Models;149
12.2.4.1;Transport Delay;149
12.2.4.2;Inertial Delay;150
12.2.4.3;Wire Delay;150
12.2.4.4;Functional Element Delay Model;151
12.3;Logic Simulation;152
12.3.1;Compiled-Code Simulation;152
12.3.1.1;Logic Optimization;152
12.3.1.2;Logic Levelization;154
12.3.1.3;Code Generation;155
12.3.2;Event-Driven Simulation;156
12.3.2.1;Nominal-Delay Event-Driven Simulation;157
12.3.3;Compiled-Code Versus Event-Driven Simulation;160
12.3.4;Hazards;161
12.3.4.1;Static Hazard Detection;162
12.3.4.2;Dynamic Hazard Detection;163
12.4;Fault Simulation;163
12.4.1;Serial Fault Simulation;164
12.4.2;Parallel Fault Simulation;166
12.4.2.1;Parallel Fault Simulation;166
12.4.2.2;Parallel-Pattern Fault Simulation;168
12.4.3;Deductive Fault Simulation;170
12.4.4;Concurrent Fault Simulation;174
12.4.5;Differential Fault Simulation;177
12.4.6;Fault Detection;179
12.4.7;Comparison of Fault Simulation Techniques;180
12.4.8;Alternatives to Fault Simulation;182
12.4.8.1;Toggle Coverage;182
12.4.8.2;Fault Sampling;182
12.4.8.3;Critical Path Tracing;183
12.4.8.4;Statistical Fault Analysis;184
12.5;Concluding Remarks;185
12.6;Exercises;186
12.7;References;189
13;4 Test Generation;192
13.1;Introduction;192
13.2;Random Test Generation;194
13.2.1;Exhaustive Testing;197
13.3;Theoretical Background: Boolean Difference;197
13.3.1;Untestable Faults;199
13.4;Designing a Stuck-At ATPG for Combinational Circuits;200
13.4.1;A Naive ATPG Algorithm;200
13.4.1.1;Backtracking;203
13.4.2;A Basic ATPG Algorithm;204
13.4.3;D Algorithm;208
13.4.4;PODEM;213
13.4.5;FAN;217
13.4.6;Static Logic Implications;218
13.4.7;Dynamic Logic Implications;222
13.5;Designing a Sequential ATPG;225
13.5.1;Time Frame Expansion;225
13.5.2;5-Valued Algebra Is Insufficient;227
13.5.3;Gated Clocks and Multiple Clocks;228
13.6;Untestable Fault Identification;231
13.6.1;Multiple-Line Conflict Analysis;234
13.7;Designing a Simulation-Based ATPG;238
13.7.1;Overview;239
13.7.2;Genetic-Algorithm-Based ATPG;239
13.7.2.1;Issues Concerning the GA Population;243
13.7.2.2;Issues Concerning GA Parameters;244
13.7.2.3;Issues Concerning the Fitness Function;244
13.7.2.4;CASE Studies;246
13.8;Advanced Simulation-Based ATPG;249
13.8.1;Seeding the GA with Helpful Sequences;249
13.8.2;Logic-Simulation-Based ATPG;253
13.8.3;Spectrum-Based ATPG;256
13.9;Hybrid Deterministic and Simulation-Based ATPG;257
13.9.1;ALT-TEST Hybrid;259
13.10;ATPG for Non-Stuck-At Faults;262
13.10.1;Designing an ATPG That Captures Delay Defects;262
13.10.1.1;Classification of Path-Delay Faults;264
13.10.1.2;ATPG for Path-Delay Faults;267
13.10.2;ATPG for Transition Faults;269
13.10.3;Transition ATPG Using Stuck-At ATPG;271
13.10.4;Transition ATPG Using Stuck-At Vectors;271
13.10.4.1;Transition Test Chains via Weighted Transition Graph;272
13.10.5;Bridging Fault ATPG;275
13.11;Other Topics in Test Generation;277
13.11.1;Test Set Compaction;277
13.11.2;N-Detect ATPG;278
13.11.3;ATPG for Acyclic Sequential Circuits;278
13.11.4;IDDQ Testing;278
13.11.5;Designing a High-Level ATPG;279
13.12;Concluding Remarks;279
13.13;Exercises;280
13.14;References;287
14;5 Logic Built-In Self-Test;294
14.1;Introduction;295
14.2;BIST Design Rules;297
14.2.1;Unknown Source Blocking;298
14.2.1.1;Analog Blocks;298
14.2.1.2;Memories and Non-Scan Storage Elements;299
14.2.1.3;Combinational Feedback Loops;299
14.2.1.4;Asynchronous Set/Reset Signals;299
14.2.1.5;Tristate Buses;300
14.2.1.6;False Paths;301
14.2.1.7;Critical Paths;301
14.2.1.8;Multiple-Cycle Paths;301
14.2.1.9;Floating Ports;301
14.2.1.10;Bidirectional I/O Ports;302
14.2.2;Re-Timing;302
14.3;Test Pattern Generation;302
14.3.1;Exhaustive Testing;306
14.3.1.1;Binary Counter;306
14.3.1.2;Complete LFSR;306
14.3.2;Pseudo-Random Testing;308
14.3.2.1;Maximum-Length LFSR;309
14.3.2.2;Weighted LFSR;309
14.3.2.3;Cellular Automata;309
14.3.3;Pseudo-Exhaustive Testing;312
14.3.3.1;Verification Testing;313
14.3.3.2;Segmentation Testing;318
14.3.4;Delay Fault Testing;319
14.3.5;Summary;320
14.4;Output Response Analysis;321
14.4.1;Ones Count Testing;322
14.4.2;Transition Count Testing;322
14.4.3;Signature Analysis;323
14.4.3.1;Serial Signature Analysis;323
14.4.3.2;Parallel Signature Analysis;325
14.5;Logic BIST Architectures;327
14.5.1;BIST Architectures for Circuits without Scan Chains;327
14.5.1.1;A Centralized and Separate Board-Level BIST Architecture;327
14.5.1.2;Built-In Evaluation and Self-Test (BEST);328
14.5.2;BIST Architectures for Circuits with Scan Chains;328
14.5.2.1;LSSD On-Chip Self-Test;328
14.5.2.2;Self-Testing Using MISR and Parallel SRSG;329
14.5.3;BIST Architectures Using Register Reconfiguration;329
14.5.3.1;Built-In Logic Block Observer;330
14.5.3.2;Modified Built-In Logic Block Observer;331
14.5.3.3;Concurrent Built-In Logic Block Observer;331
14.5.3.4;Circular Self-Test Path (CSTP);333
14.5.4;BIST Architectures Using Concurrent Checking Circuits;334
14.5.4.1;Concurrent Self-Verification;334
14.5.5;Summary;335
14.6;Fault Coverage Enhancement;335
14.6.1;Test Point Insertion;336
14.6.1.1;Test Point Placement;337
14.6.1.2;Control Point Activation;338
14.6.2;Mixed-Mode BIST;339
14.6.2.1;ROM Compression;339
14.6.2.2;LFSR Reseeding;339
14.6.2.3;Embedding Deterministic Patterns;340
14.6.3;Hybrid BIST;340
14.7;BIST Timing Control;341
14.7.1;Single-Capture;341
14.7.1.1;One-Hot Single-Capture;341
14.7.1.2;Staggered Single-Capture;342
14.7.2;Skewed-Load;342
14.7.2.1;One-Hot Skewed-Load;343
14.7.2.2;Aligned Skewed-Load;343
14.7.2.3;Staggered Skewed-Load;345
14.7.3;Double-Capture;346
14.7.3.1;One-Hot Double-Capture;346
14.7.3.2;Aligned Double-Capture;347
14.7.3.3;Staggered Double-Capture;348
14.7.4;Fault Detection;348
14.8;A Design Practice;350
14.8.1;BIST Rule Checking and Violation Repair;351
14.8.2;Logic BIST System Design;351
14.8.2.1;Logic BIST Architecture;351
14.8.2.2;TPG and ORA;352
14.8.2.3;Test Controller;353
14.8.2.4;Clock Gating Block;354
14.8.2.5;Re-Timing Logic;356
14.8.2.6;Fault Coverage Enhancing Logic and Diagnostic Logic;356
14.8.3;RTL BIST Synthesis;357
14.8.4;Design Verification and Fault Coverage Enhancement;357
14.9;Concluding Remarks;358
14.10;Exercises;358
14.11;Acknowledgments;362
14.12;References;362
15;6 Test Compression;372
15.1;Introduction;373
15.2;Test Stimulus Compression;375
15.2.1;Code-Based Schemes;376
15.2.1.1;Dictionary Code (Fixed-to-Fixed);376
15.2.1.2;Huffman Code (Fixed-to-Variable);377
15.2.1.3;Run-Length Code (Variable-to-Fixed);380
15.2.1.4;Golomb Code (Variable-to-Variable);381
15.2.2;Linear-Decompression-Based Schemes;382
15.2.2.1;Combinational Linear Decompressors;386
15.2.2.2;Fixed-Length Sequential Linear Decompressors;386
15.2.2.3;Variable-Length Sequential Linear Decompressors .;387
15.2.2.4;Combined Linear and Nonlinear Decompressors;388
15.2.3;Broadcast-Scan-Based Schemes;390
15.2.3.1;Broadcast Scan;390
15.2.3.2;Illinois Scan;391
15.2.3.3;Multiple-Input Broadcast Scan;393
15.2.3.4;Reconfigurable Broadcast Scan;393
15.2.3.5;Virtual Scan;394
15.3;Test Response Compaction;395
15.3.1;Space Compaction;398
15.3.1.1;Zero-Aliasing Linear Compaction;398
15.3.1.2;X-Compact;400
15.3.1.3;X-Blocking;402
15.3.1.4;X-Masking;403
15.3.1.5;X-Impact;404
15.3.2;Time Compaction;405
15.3.3;Mixed Time and Space Compaction;406
15.4;Industry Practices;407
15.4.1;OPMISR+;408
15.4.2;Embedded Deterministic Test;410
15.4.3;VirtualScan and UltraScan;413
15.4.4;Adaptive Scan;416
15.4.5;ETCompression;417
15.4.6;Summary;419
15.5;Concluding Remarks;419
15.6;Exercises;420
15.7;Acknowledgments;421
15.8;References;422
16;7 Logic Diagnosis;428
16.1;Introduction;428
16.2;Combinational Logic Diagnosis;432
16.2.1;Cause–Effect Analysis;432
16.2.1.1;Compaction and Compression of Fault Dictionary;434
16.2.2;Effect–Cause Analysis;436
16.2.2.1;Structural Pruning;438
16.2.2.2;Backtrace Algorithm;439
16.2.2.3;Inject-and-Evaluate Paradigm;440
16.2.3;Chip-Level Strategy;449
16.2.3.1;Direct Partitioning;449
16.2.3.2;Two-Phase Strategy;451
16.2.3.3;Overall Chip-Level Diagnostic Flow;455
16.2.4;Diagnostic Test Pattern Generation;456
16.2.5;Summary of Combinational Logic Diagnosis;457
16.3;Scan Chain Diagnosis;458
16.3.1;Preliminaries for Scan Chain Diagnosis;458
16.3.2;Hardware-Assisted Method;461
16.3.3;Modified Inject-and-Evaluate Paradigm;463
16.3.4;Signal-Profiling-Based Method;465
16.3.4.1;Diagnostic Test Sequence Selection;465
16.3.4.2;Run-and-Scan Test Application;465
16.3.4.3;Why Functional Sequence?;466
16.3.4.4;Profiling-Based Analysis;468
16.3.5;Summary of Scan Chain Diagnosis;472
16.4;Logic BIST Diagnosis;473
16.4.1;Overview of Logic BIST Diagnosis;473
16.4.2;Interval-Based Methods;474
16.4.3;Masking-Based Methods;477
16.5;Concluding Remarks;480
16.6;Exercises;481
16.7;Acknowledgments;484
16.8;References;485
17;8 Memory Testing and Built-In Self-Test;492
17.1;Introduction;493
17.2;RAM Functional Fault Models and Test Algorithms;494
17.2.1;RAM Functional Fault Models;494
17.2.2;RAM Dynamic Faults;496
17.2.3;Functional Test Patterns and Algorithms;497
17.2.4;March Tests;500
17.2.5;Comparison of RAM Test Patterns;502
17.2.6;Word-Oriented Memory;504
17.2.7;Multi-Port Memory;504
17.3;RAM Fault Simulation and Test Algorithm Generation;506
17.3.1;Fault Simulation;507
17.3.2;RAMSES;508
17.3.3;Test Algorithm Generation by Simulation;511
17.4;Memory Built-In Self-Test;519
17.4.1;RAM Specification and BIST Design Strategy;520
17.4.2;BIST Architectures and Functions;524
17.4.3;BIST Implementation;526
17.4.4;BRAINS: A RAM BIST Compiler;531
17.5;Concluding Remarks;539
17.6;Exercises;540
17.7;Acknowledgments;544
17.8;References;544
18;9 Memory Diagnosis and Built-In Self-Repair;548
18.1;Introduction;549
18.1.1;Why Memory Diagnosis?;549
18.1.2;Why Memory Repair?;549
18.2;Refined Fault Models and Diagnostic Test Algorithms;549
18.3;BIST with Diagnostic Support;552
18.3.1;Controller;552
18.3.2;Test Pattern Generator;554
18.3.3;Fault Site Indicator (FSI);555
18.4;RAM Defect Diagnosis and Failure Analysis;557
18.5;RAM Redundancy Analysis Algorithms;560
18.5.1;Conventional Redundancy Analysis Algorithms;560
18.5.2;The Essential Spare Pivoting Algorithm;562
18.5.3;Repair Rate and Overhead;566
18.6;Built-In Self-Repair;568
18.6.1;Redundancy Organization;568
18.6.2;BISR Architecture and Procedure;569
18.6.3;BIST Module;572
18.6.4;BIRA Module;573
18.6.5;An Industrial Case;576
18.6.6;Repair Rate and Yield;579
18.7;Concluding Remarks;583
18.8;Exercises;583
18.9;Acknowledgments;584
18.10;References;584
19;10 Boundary Scan and Core-Based Testing;588
19.1;Introduction;589
19.1.1;IEEE 1149 Standard Family;589
19.1.2;Core-Based Design and Test Considerations;590
19.2;Digital Boundary Scan (IEEE Std. 1149.1);592
19.2.1;Basic Concept;592
19.2.2;Overall 1149.1 Test Architecture and Operations;593
19.2.3;Test Access Port and Bus Protocols;595
19.2.4;Data Registers and Boundary-Scan Cells;596
19.2.5;TAP Controller;598
19.2.6;Instruction Register and Instruction Set;600
19.2.7;Boundary-Scan Description Language;605
19.2.8;On-Chip Test Support with Boundary Scan;605
19.2.9;Board and System-Level Boundary-Scan Control Architectures;607
19.3;Boundary Scan for Advanced Networks (IEEE 1149.6);610
19.3.1;Rationale for 1149.6;610
19.3.2;1149.6 Analog Test Receiver;612
19.3.3;1149.6 Digital Driver Logic;612
19.3.4;1149.6 Digital Receiver Logic;613
19.3.5;1149.6 Test Access Port (TAP);615
19.3.6;Summary;616
19.4;Embedded Core Test Standard (IEEE Std. 1500);616
19.4.1;SOC (System-on-Chip) Test Problems;616
19.4.2;Overall Architecture;618
19.4.3;Wrapper Components and Functions;620
19.4.4;Instruction Set;628
19.4.5;Core Test Language (CTL);632
19.4.6;Core Test Supporting and System Test Configurations;634
19.4.7;Hierarchical Test Control and Plug-and-Play;637
19.5;Comparisons between the 1500 and 1149.1 Standards;641
19.6;Concluding Remarks;642
19.7;Exercises;643
19.8;Acknowledgments;645
19.9;References;645
20;11 Analog and Mixed-Signal Testing;650
20.1;Introduction;650
20.1.1;Analog Circuit Properties;651
20.1.1.1;Continuous Signals;652
20.1.1.2;Large Range of Circuits;652
20.1.1.3;Nonlinear Characteristics;652
20.1.1.4;Feedback Ambiguity;653
20.1.1.5;Complicated Cause–Effect Relationship;653
20.1.1.6;Absence of Suitable Fault Model;653
20.1.1.7;Requirement for Accurate Instruments for Measuring Analog Signals;654
20.1.2;Analog Defect Mechanisms and Fault Models;654
20.1.2.1;Hard Faults;656
20.1.2.2;Soft Faults;656
20.2;Analog Circuit Testing;658
20.2.1;Analog Test Approaches;658
20.2.2;Analog Test Waveforms;660
20.2.3;DC Parametric Testing;662
20.2.3.1;Open-Loop Gain Measurement;663
20.2.3.2;Unit Gain Bandwidth Measurement;664
20.2.3.3;Common Mode Rejection Ratio Measurement;665
20.2.3.4;Power Supply Rejection Ratio Measurement;666
20.2.4;AC Parametric Testing;666
20.2.4.1;Maximal Output Amplitude Measurement;667
20.2.4.2;Frequency Response Measurement;668
20.2.4.3;SNR and Distortion Measurement;670
20.2.4.4;Intermodulation Distortion Measurement;672
20.3;Mixed-Signal Testing;672
20.3.1;Introduction to Analog–Digital Conversion;673
20.3.2;ADC and DAC Circuit Structure;675
20.3.2.1;DAC Circuit Structure;677
20.3.2.2;ADC Circuit Structure;677
20.3.3;ADC/DAC Specification and Fault Models;678
20.3.4;IEEE 1057 Standard;683
20.3.5;Time-Domain ADC Testing;685
20.3.5.1;Code Bins;685
20.3.5.2;Code Transition Level Test (Static);686
20.3.5.3;Code Transition Level Test (Dynamic);686
20.3.5.4;Gain and Offset Test;687
20.3.5.5;Linearity Error and Maximal Static Error;688
20.3.5.6;Sine Wave Curve-Fit Test;689
20.3.6;Frequency-Domain ADC Testing;689
20.4;IEEE 1149.4 Standard for a Mixed-Signal Test Bus;689
20.4.1;IEEE 1149.4 Overview;690
20.4.1.1;Scope of the Standard;691
20.4.2;IEEE 1149.4 Circuit Structures;692
20.4.3;IEEE 1149.4 Instructions;696
20.4.3.1;Mandatory Instructions;696
20.4.3.2;Optional Instructions;696
20.4.4;IEEE 1149.4 Test Modes;697
20.4.4.1;Open/Short Interconnect Testing;697
20.4.4.2;Extended Interconnect Measurement;698
20.4.4.3;Complex Network Measurement;702
20.4.4.4;High-Performance Configuration;703
20.5;Concluding Remarks;704
20.6;Exercises;704
20.7;Acknowledgments;707
20.8;References;708
21;12 Test Technology Trends in the Nanometer Age;710
21.1;Test Technology Roadmap;711
21.2;Delay Testing;716
21.2.1;Test Application Schemes for Testing Delay Defects;717
21.2.2;Delay Fault Models;718
21.2.3;Summary;721
21.3;Coping with Physical Failures, Soft Errors, and Reliability Issues;723
21.3.1;Signal Integrity and Power Supply Noise;723
21.3.1.1;Integrity Loss Fault Model;724
21.3.1.2;Location;725
21.3.1.3;Pattern Generation;725
21.3.1.4;Sensing and Readout;726
21.3.2;Parametric Defects, Process Variations, and Yield;727
21.3.2.1;Defect-Based Test;728
21.3.3;Soft Errors;729
21.3.4;Fault Tolerance;732
21.3.5;Defect and Error Tolerance;736
21.4;FPGA Testing;737
21.4.1;Impact of Programmability;737
21.4.2;Testing Approaches;739
21.4.3;Built-In Self-Test of Logic Resources;739
21.4.4;Built-In Self-Test of Routing Resources;740
21.4.5;Recent Trends;741
21.5;MEMS Testing;742
21.5.1;Basic Concepts for Capacitive MEMS Devices;742
21.5.2;MEMS Built-In Self-Test;744
21.5.2.1;Sensitivity BIST Scheme;744
21.5.2.2;Symmetry BIST Scheme;744
21.5.2.3;A Dual-Mode BIST Technique;745
21.5.3;A BIST Example for MEMS Comb Accelerometers;747
21.5.4;Conclusions;750
21.6;High-speed I/O Testing;750
21.6.1;I/O Interface Technology and Trend;751
21.6.2;I/O Testing and Challenges;755
21.6.3;High-Performance I/O Test Solutions;756
21.6.4;Future Challenges;757
21.7;RF Testing;759
21.7.1;Core RF Building Blocks;760
21.7.2;RF Test Specifications and Measurement Procedures;761
21.7.2.1;Gain;761
21.7.2.2;Conversion Gain;762
21.7.2.3;Third-Order Intercept;762
21.7.2.4;Noise Figure;764
21.7.3;Tests for System-Level Specifications;764
21.7.3.1;Adjacent Channel Power Ratio;764
21.7.3.2;Error Vector Magnitude, Magnitude Error, and Phase Error;765
21.7.4;Current and Future Trends;766
21.7.4.1;Future Trends;767
21.7.5;Concluding Remarks;768
21.7.6;Acknowledgments;769
21.7.7;References;769
22;Index;782