On-Chip Training NPU - Algorithm, Architecture and SoC Design

2023
ISBN: 978-3-031-34239-4
Verlag: Springer Nature Switzerland

Buch, Englisch, 237 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 406 g

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Yoo, Hoi-Jun

Han, Donghyeon

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur

Inhaltsverzeichnis

Chapter 1 Introduction.- Chapter 2 A Theoretical Study on Artificial Intelligence Training.- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer.- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network.- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning.- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching.- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation.- Chapter 8 An Overview of Energy-efficient DNN Training Processors.- Chapter 9 Conclusion.

Über Autor(innen)

Donghyeon Han (S’17) received the B.S., M.S., and Ph.D. degrees from the school of electrical engineering of Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2017, 2019 and 2023, respectively. He is now the postdoctoral associate at Massachusetts Institute of Technology (MIT).

His current research interests include low-power system-on-chip design, especially focused on on-device deep neural network training accelerators and hardware-friendly deep learning algorithms. His Ph. D research resulted in several publications in ISSCC, SoVC, JSSC, TCAS-I, IEEE Micro, AICAS, Hotchips, and Coolchips.

Hoi-Jun Yoo is the KAIST ICT Endowed Chair Professor, School of Electrical Engineering, KAIST. He was the VCSEL pioneer in Bell Communications Research at Red Bank, NJ. USA and Manager of DRAM design group at Hyundai Electronics designing from 1M DRAM to 256M SDRAM.

Currently, he is a full professor of Department of Electrical Engineering atKAIST and the director of the System Design Innovation and Application Research Center (SDIA). From 2003 to 2005, he served as the full time Advisor to the Minister of Korean Ministry of Information and Communication for SoC and Next Generation Computing. His current research interests are Bio Inspired IC Design, Network on a Chip, Multimedia SoC design, Wearable Healthcare Systems, and high speed and low power memory. He has published more than 250 papers, and wrote or edited 5 books, “DRAM Design”(1997, Hongneung), “High Performance DRAM”(1999 Hongneung), “Low Power NoC for High Performance SoC Design”(2008, CRC), “Mobile 3D Graphics SoC”(2010, Wiley), and “BioMedical CMOS ICs”(Co-editing with Chris Van Hoof, 2010, Springer), and many chapters of books.

Dr. Yoo received Order of Service Merit from Korean government in 2011 for his contribution to Korean memory industry, Scientist/Engineer of this month Award from Ministry of Education, Science and Technology of Korea in 2010, Best Scholarship Awards of KAIST in 2011. He also received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, Best Research of KAIST Award in 2007, and has been co-recipients of ASP-DAC Design Award 2001, Outstanding Design Awards of 2005, 2006, 2007, 2010, 2011, 2014 A-SSCC, Student Design Contest Award of 2007, 2008, 2010, 2011 DAC/ISSCC. He has served as a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He also served as the IEEE SSCS Distinguished Lecturer ('10-'11) and the TPC chairs of ISSCC 2015, ISWC 2010 and A-SSCC 2008. He is an IEEE Fellow.