Neuro-inspired Computing Using Resistive Synaptic Devices

Softcover Nachdruck of the original 1. Auflage 2017
ISBN: 978-3-319-85368-0
Verlag: Springer International Publishing

Buch, Englisch, 269 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 4853 g

This book summarizes the recent breakthroughs in hardware implementation of neuro-inspired computing using resistive synaptic devices. The authors describe how two-terminal solid-state resistive memories can emulate synaptic weights in a neural network. Readers will benefit from state-of-the-art summaries of resistive synaptic devices, from the individual cell characteristics to the large-scale array integration. This book also discusses peripheral neuron circuits design challenges and design strategies. Finally, the authors describe the impact of device non-ideal properties (e.g. noise, variation, yield) and their impact on the learning performance at the system-level, using a device-algorithm co-design methodology.

Zielgruppe

Research

Autoren/Hrsg.

Yu, Shimeng

Fachgebiete

• Mathematik | Informatik EDV | Informatik Informatik Künstliche Intelligenz
• Technische Wissenschaften Technik Allgemein Bionik, Biomimetik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Chapter1: Introduction to Neuro-Inspired Computing using Resistive Synaptic Devices.- Part I: Device-level Demonstrations of Resistive Synaptic Devices.- Chapter2: Phase Change Memory based Synaptic Devices.- Chapter3: Pr0.7Ca0.3MnO3 (PCMO) based Synaptic Devices.- Chapter4: TaOx/TiO2 based Synaptic Devices.- Part II: Array-level Demonstrations of Resistive Synaptic Devices and Neural Networks.- Chapter5: Training and Inference in Hopfield Network using 10×10 Phase Change Synaptic Array.- Chapter6: Experimental Demonstration of Firing-Rate Neural Networks based on Metal-Oxide Memristive Crossbars.- Chapter7: Weight Tuning of Resistive Synaptic Devices and Convolution Kernel Operation on 12×12 Cross-Point Array.- Chapter8: Spiking Neural Network with 256×256 PCM Array.- Part III: Circuit, Architecture and Algorithm-level Design of Resistive Synaptic Devices based Neuromorphic System.- Chapter9: Peripheral Circuit Design Considerations of Neuro-inspired Architectures.- Chapter10: Processing-in-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms.- Chapter11: Multi-layer Perceptron Algorithm: Impact of Non-Ideal Conductance and Area-Efficient Peripheral Circuits.- Chapter12: Impact of Non-Ideal Resistive Synaptic Device Behaviors on Implementation of Sparse Coding Algorithm.- Chapter13: Binary OxRAM/CBRAM Memories for Efficient Implementations of Embedded Neuromorphic Circuits.

Über Autor(innen)

Shimeng Yu He received the B.S. degree in microelectronics from Peking University, Beijing, China, in 2009 and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, USA, in 2011 and in 2013, respectively. He joined Arizona State University, Tempe, AZ, USA, as an assistant professor of electrical engineering and computer engineering in 2013.
His research interests are emerging nano-devices and circuits with a focus on the resistive memories for different applications including neuro-inspired computing, monolithic 3D integration, hardware security, radiation-hard electronics, etc. He has published more than 50 journal papers and more than 90 conference papers with citations of more than 4000 and H-index of 28 according to Google Scholar.
Among his honors, he is a recipient of the Stanford Graduate Fellowship from 2009 to 2012, the IEEE Electron Devices Society Masters Student Fellowship in2010, the IEEE Electron Devices Society Ph.D. Student Fellowship in 2012, the DOD-DTRA Young Investigator Award in 2015, and the NSF Faculty Early CAREER Award in 2016 on the topic of scaling up resistive synaptic arrays for neuro-inspired computing.
He did summer internship in IMEC, Belgium, in 2011 and the IBM TJ Watson Research Center in 2012. He held visiting faculty position in the Air Force Research Laboratory in 2016. He has been serving the Technical Committee of Nanoelectronics and Gigascale Systems, IEEE Circuits and Systems Society, since 2014.