Generating Hardware Assertion Checkers

For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
1. Auflage. Softcover version of original hardcover Auflage 2008
ISBN: 978-90-481-7922-0
Verlag: Springer Netherlands

Buch, Englisch, 280 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 458 g

Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.

This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.

Zielgruppe

Research

Autoren/Hrsg.

Zilic, Zeljko

Boulé, Marc

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Informatik
• Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Prozedurale Programmierung

Inhaltsverzeichnis

Assertions and the Verification Landscape.- Basic Techniques Behind Assertion Checkers.- PSL and SVA Assertion Languages.- Automata for Assertion Checkers.- Construction of PSL Assertion Checkers.- Enhanced Features and Uses of PSL Checkers.- Evaluating and Verifying PSL Assertion Checkers.- Checkers for SystemVerilog Assertions.- Conclusions and Future Work.